4 files changed, 68 insertions, 20 deletions

diff --git a/src/storage/cache.cc b/src/storage/cache.cc
index 67cedda..ec14ce6 100644
--- a/src/storage/cache.cc
+++ b/src/storage/cache.cc
@@ -1,22 +1,67 @@
 #include "cache.h"
 #include "definitions.h"
 #include "response.h"
+#include "utils.h"
 #include <bits/stdc++.h>
 
 Cache::Cache(int lines, Storage *lower, int delay)
 {
 	this->data = new std::vector<std::array<signed int, LINE_SIZE>>;
-	this->data->resize(lines);
+	this->data->resize(L1_CACHE_SIZE);
 	this->lower = lower;
 	this->delay = delay;
-	this->lower = nullptr;
+	this->meta.fill({-1});
 }
 
 Cache::~Cache() { delete this->data; }
 
 Response Cache::write(Accessor accessor, signed int data, int address)
 {
+	Response r = WAIT;
+
+	/* Do this first--then process the first cycle immediately. */
+	if (this->requester == IDLE)
+		this->requester = accessor;
+
+	if (this->requester == accessor) {
+		fetch_resource(address);
+		if (this->is_waiting == true)
+			r = BLOCKED;
+		else if (this->wait_time == 0) {
+			r = OK;
+		}
+	}
+
+	return r;
+}
+
+Response Cache::read(
+	Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
+{
 	return WAIT;
 }
 
-Response Cache::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) { return WAIT; }
+void Cache::fetch_resource(int expected)
+{
+	Response r = OK;
+	int etag, index, atag;
+	std::array<signed int, LINE_SIZE> actual;
+	std::array<int, 2> meta;
+
+	get_bit_fields(expected, &etag, &index, nullptr);
+	meta = this->meta.at(index);
+
+	if (atag != etag) {
+		// address not in cache
+		if (this->meta[index][0]) {
+			// occupant is dirty
+			// TODO
+			r = WAIT;
+		} else {
+			actual = this->data->at(index);
+			r = this->lower->read(L1CACHE, expected, actual);
+		}
+	}
+
+	this->is_waiting = (r == OK) ? false : true;
+}
diff --git a/src/storage/dram.cc b/src/storage/dram.cc
index 0db4c35..23dedc0 100644
--- a/src/storage/dram.cc
+++ b/src/storage/dram.cc
@@ -15,6 +15,14 @@ Dram::Dram(int lines, int delay)
 
 Dram::~Dram() { delete this->data; }
 
+void Dram::do_write(signed data, int address)
+{
+	int line = address / LINE_SIZE;
+	int word = address % LINE_SIZE;
+
+	this->data->at(line).at(word) = data;
+}
+
 Response Dram::write(Accessor accessor, signed int data, int address)
 {
 	Response r = WAIT;
@@ -38,12 +46,15 @@ Response Dram::write(Accessor accessor, signed int data, int address)
 	return r;
 }
 
-void Dram::do_read(std::array<signed int, LINE_SIZE>& data_line, int address){
+void Dram::do_read(std::array<signed int, LINE_SIZE> &data_line, int address)
+{
 	int line = address / LINE_SIZE;
 	data_line = this->data->at(line);
 }
 
-Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_SIZE>& data) { 
+Response Dram::read(
+	Accessor accessor, int address, std::array<signed int, LINE_SIZE> &data)
+{
 	Response r = WAIT;
 	if (this->requester == IDLE)
 		this->requester = accessor;
@@ -53,5 +64,5 @@ Response Dram::read(Accessor accessor, int address, std::array<signed int, LINE_
 			r = OK;
 		}
 	}
-	return r; 
- }
+	return r;
+}
diff --git a/src/storage/storage.cc b/src/storage/storage.cc
index e3067a2..61531d1 100644
--- a/src/storage/storage.cc
+++ b/src/storage/storage.cc
@@ -13,20 +13,12 @@ Storage::view(int base, int lines)
 	return ret;
 }
 
-void Storage::do_write(signed data, int address)
-{
-	int line = address / LINE_SIZE;
-	int word = address % LINE_SIZE;
-
-	this->data->at(line).at(word) = data;
-}
-
 void Storage::resolve()
 {
 	if (this->wait_time == 0) {
 		this->requester = IDLE;
 		this->wait_time = delay;
-	} else if (this->requester != IDLE) {
+	} else if (this->requester != IDLE && !this->is_waiting) {
 		--this->wait_time;
 	}
 }
diff --git a/src/utils/utils.cc b/src/utils/utils.cc
index b4bdb2f..dfeb2b3 100644
--- a/src/utils/utils.cc
+++ b/src/utils/utils.cc
@@ -1,11 +1,11 @@
-#include "definitions.h"
 #include "utils.h"
+#include "definitions.h"
 
 void get_bit_fields(int address, int *tag, int *index, int *offset)
 {
 	*tag =
-		MID(address, LINE_SPEC + L1_CACHE_SPEC,
+		GET_MID_BITS(address, LINE_SPEC + L1_CACHE_SPEC,
 			MEM_SPEC + LINE_SPEC + L1_CACHE_SPEC);
-	*index = MID(address, LINE_SPEC, L1_CACHE_SPEC + LINE_SPEC);
-	*offset = LAST(address, LINE_SPEC);
+	*index = GET_MID_BITS(address, LINE_SPEC, L1_CACHE_SPEC + LINE_SPEC);
+	*offset = GET_LS_BITS(address, LINE_SPEC);
 }