index
:
RAM.git
master
'RAM Acts Magically' a memory simulator supporting configurable cache levels and ways
bd
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
storage
/
dram.cc
Age
Commit message (
Collapse
)
Author
2025-03-26
Add fetch stage implementation, tests, program loading, DTO object
bd
2025-03-22
Remove manual clock advancing / resolution from storage devices
bd
2025-03-21
add 'process' function to handle boilerplate on every request
bd
2025-03-21
Small cleanups to up a lot of inplementation details
bd
2025-03-20
Rewrite all Dram tests to use Fixture
bd
2025-03-11
Fix issue where fetch_resource did not update cache data
bd
2025-03-11
Call memory wrapping functions properly
bd
2025-03-11
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-11
Rename read/write to read_line and write_word
bd
2025-03-11
Pad memory address output with trailing zeros
bd
2025-03-11
Clarify size of mem and cache in definitions, CLI print invalid tags
bd
2025-03-11
Resolving conflicts
Siddarth-Suresh
2025-03-11
support for reading word, writing line to storage, dirty cache eviction, ↵
Siddarth-Suresh
cache load
2025-03-11
Write line, dirty cache eviction, cache load word/line (for future ↵
Siddarth-Suresh
multilevel cache implementation)
2025-03-11
fix namespace issues with match function
bd
2025-03-11
cli display clock cycle, parse ';' delimited commands
bd
2025-03-10
overload << operator for dram
bd
2025-03-09
Properly set cache metadata when a value is loaded
bd
2025-03-09
initialize wait_time in dram to resolve undefined behavior
bd
2025-03-09
Untested implementation for loading absent data into cache
bd
2025-03-09
Move do_write to dram.h, is_blocked flag
bd
2025-03-09
Code review comments
Siddarth-Suresh
2025-03-09
Implement dram load
Siddarth-Suresh
2025-03-08
Properly initialize the requester
bd
2025-03-08
Remove queue in storage.h
bd
2025-03-08
Fix bug where wait_time would decrease while idle
bd
2025-03-08
enforce single unit per clock cycle, order to serve storage requests
bd
2025-03-08
Refactor function return scheme
bd
2025-03-06
Allow sidedoor free access to writing memory
bd
2025-03-06
dram implement delay and conflicting request logic
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
bd
2025-03-05
whitespace
bd
2025-03-05
constructors + method declarations for cache, dram, reponse, storage
bd
2025-03-04
Impartial storage/dram classes
bd