From 5cf5ebce233cc49cc04ac8c7713e12e87bab7798 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 18:28:08 -0400 Subject: Move do_write to dram.h, is_blocked flag --- inc/storage.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'inc/storage.h') diff --git a/inc/storage.h b/inc/storage.h index 1fb41b0..9707041 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -32,7 +32,10 @@ class Storage * @return a status code reflecting the state of the request, and the * data being returned. */ - virtual Response read(Accessor accessor, int address, std::array& data) = 0; + virtual Response read( + Accessor accessor, + int address, + std::array &data) = 0; /** * Sidedoor view of `lines` of memory starting at `base`. * @param The base line to start getting memory from. @@ -47,10 +50,6 @@ class Storage void resolve(); protected: - /** - * Helper for `write`. - */ - void do_write(signed int, int); /** * The data currently stored in this level of storage. */ @@ -73,6 +72,11 @@ class Storage * The number of cycles until the current request is completed. */ int wait_time; + /** + * A flag indicating whether this level of storage is currently blocked by a + * lower level. + */ + int is_blocked; }; #endif /* STORAGE_H_INCLUDED */ -- cgit v1.2.3 From 9bd18b0499d5096bc91b09a2d26e700ca1560de4 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 20:15:45 -0400 Subject: Untested implementation for loading absent data into cache --- inc/cache.h | 12 ++++++------ inc/storage.h | 6 +++--- src/storage/cache.cc | 38 ++++++++++++++++++++++++++++++++------ src/storage/dram.cc | 11 +++++++---- src/storage/storage.cc | 2 +- 5 files changed, 49 insertions(+), 20 deletions(-) (limited to 'inc/storage.h') diff --git a/inc/cache.h b/inc/cache.h index a317f5d..c8c9736 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -30,17 +30,17 @@ class Cache : public Storage /** * Fetches `address` from a lower level of storage if it is not already * present. If it is not, temporarily sets the is_blocked attribute of this - * cache level to true. + * cache level to true, and the victim line is chosen/written back. * @param the address that must be present in cache. */ void fetch_resource(int address); /** - * An array of paired bits. - * If the least significant bit of an element is set, the corresponding - * element in `data` is invalid. If the most significant bit of an element - * is set, the corresponding element in `data` is dirty. + * An array of metadata about elements in `data`. + * If the first value of an element is negative, the corresponding + * element in `data` is invalid. If the most second value of an element + * is nonzero, the corresponding element in `data` is dirty. */ - std::array, L1_CACHE_SIZE> stat; + std::array, L1_CACHE_SIZE> meta; }; #endif /* CACHE_H_INCLUDED */ diff --git a/inc/storage.h b/inc/storage.h index 9707041..793b982 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -73,10 +73,10 @@ class Storage */ int wait_time; /** - * A flag indicating whether this level of storage is currently blocked by a - * lower level. + * A flag indicating whether this level of storage is currently waiting for + * a lower level. */ - int is_blocked; + int is_waiting; }; #endif /* STORAGE_H_INCLUDED */ diff --git a/src/storage/cache.cc b/src/storage/cache.cc index e0eaf58..ec14ce6 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -1,6 +1,7 @@ #include "cache.h" #include "definitions.h" #include "response.h" +#include "utils.h" #include Cache::Cache(int lines, Storage *lower, int delay) @@ -9,8 +10,7 @@ Cache::Cache(int lines, Storage *lower, int delay) this->data->resize(L1_CACHE_SIZE); this->lower = lower; this->delay = delay; - for (int i = 0; i < L1_CACHE_SIZE; ++i) - this->stat[i] = 0b01; + this->meta.fill({-1}); } Cache::~Cache() { delete this->data; } @@ -25,8 +25,9 @@ Response Cache::write(Accessor accessor, signed int data, int address) if (this->requester == accessor) { fetch_resource(address); - if (this->wait_time == 0) { - // this->do_write(data, address); + if (this->is_waiting == true) + r = BLOCKED; + else if (this->wait_time == 0) { r = OK; } } @@ -34,8 +35,33 @@ Response Cache::write(Accessor accessor, signed int data, int address) return r; } -Response Cache::read(Accessor accessor, int address, std::array& data) { return WAIT; } +Response Cache::read( + Accessor accessor, int address, std::array &data) +{ + return WAIT; +} + +void Cache::fetch_resource(int expected) +{ + Response r = OK; + int etag, index, atag; + std::array actual; + std::array meta; -void Cache::fetch_resource(int address) { + get_bit_fields(expected, &etag, &index, nullptr); + meta = this->meta.at(index); + + if (atag != etag) { + // address not in cache + if (this->meta[index][0]) { + // occupant is dirty + // TODO + r = WAIT; + } else { + actual = this->data->at(index); + r = this->lower->read(L1CACHE, expected, actual); + } + } + this->is_waiting = (r == OK) ? false : true; } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index e3f3c9a..23dedc0 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -46,12 +46,15 @@ Response Dram::write(Accessor accessor, signed int data, int address) return r; } -void Dram::do_read(std::array& data_line, int address){ +void Dram::do_read(std::array &data_line, int address) +{ int line = address / LINE_SIZE; data_line = this->data->at(line); } -Response Dram::read(Accessor accessor, int address, std::array& data) { +Response Dram::read( + Accessor accessor, int address, std::array &data) +{ Response r = WAIT; if (this->requester == IDLE) this->requester = accessor; @@ -61,5 +64,5 @@ Response Dram::read(Accessor accessor, int address, std::arraywait_time == 0) { this->requester = IDLE; this->wait_time = delay; - } else if (this->requester != IDLE && !this->is_blocked) { + } else if (this->requester != IDLE && !this->is_waiting) { --this->wait_time; } } -- cgit v1.2.3