From 2b458c01aca16e26939e169f1b545982e0f8626f Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 12:05:12 -0400 Subject: Add bitset field to cache.h for keeping track of write/validity --- src/storage/cache.cc | 20 +++++++++++++++++--- src/utils/utils.cc | 2 +- 2 files changed, 18 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/storage/cache.cc b/src/storage/cache.cc index bbefb2a..bf1126a 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -6,17 +6,31 @@ Cache::Cache(int lines, Storage *lower, int delay) { this->data = new std::vector>; - this->data->resize(lines); + this->data->resize(L1_CACHE_SIZE); this->lower = lower; this->delay = delay; - this->lower = nullptr; + for (int i = 0; i < L1_CACHE_SIZE; ++i) + this->stat[i] = 0b01; } Cache::~Cache() { delete this->data; } Response Cache::write(Accessor accessor, signed int data, int address) { - return WAIT; + Response r = WAIT; + + /* Do this first--then process the first cycle immediately. */ + if (this->requester == IDLE) + this->requester = accessor; + + if (this->requester == accessor) { + if (this->wait_time == 0) { + this->do_write(data, address); + r = OK; + } + } + + return r; } Response Cache::read(Accessor accessor, int address) { return WAIT; } diff --git a/src/utils/utils.cc b/src/utils/utils.cc index b4bdb2f..52be177 100644 --- a/src/utils/utils.cc +++ b/src/utils/utils.cc @@ -1,5 +1,5 @@ -#include "definitions.h" #include "utils.h" +#include "definitions.h" void get_bit_fields(int address, int *tag, int *index, int *offset) { -- cgit v1.2.3 From fcf0358b0597b733f36b0c862bf18a98efdea224 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 16:25:20 -0400 Subject: Improve documentation in definitions.h --- inc/definitions.h | 38 +++++++++++++++++++++++++++++++------- src/utils/utils.cc | 6 +++--- 2 files changed, 34 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/inc/definitions.h b/inc/definitions.h index 4b01be9..877065e 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -2,25 +2,49 @@ #define DEFINITIONS_H #include -/* The number of bits to specify a word in a line +/** + * The number of bits to specify a word in a line */ #define LINE_SPEC 2 +/** + * The total number of words in a line + */ #define LINE_SIZE (int)pow(2, 2) -/* The number of bits to specify a memory line - * (/ (expt 2 15) 4) +/** + * The number of bits to specify a memory line + * calculated as: (/ (expt 2 15) 4) */ #define MEM_SPEC 13 +/** + * The total number of words in memory + */ #define MEM_SIZE (int)pow(2, MEM_SPEC) -/* The number of bits to specify a l1 cache line +/** + * The number of bits to specify a l1 cache line */ #define L1_CACHE_SPEC 5 +/** + * The total number of words in l1 cache + */ #define L1_CACHE_SIZE (int)pow(2, L1_CACHE_SPEC) -/* Parses some bits. +/** + * Return the N least-significant bits from integer K using a bit mask + * @param the integer to be parsed + * @param the number of bits to be parsed + * @return the N least-significant bits from K + */ +#define GET_LS_BITS(k, n) ((k) & ((1 << (n)) - 1)) +/** + * Return the bits from integer K starting at N and ending at M using a bit + * mask + * @param the integer to be parsed + * @param the index of the starting bit to be parsed + * @param the index of the ending bit to be parsed + * @return a section of bits from K */ -#define LAST(k, n) ((k) & ((1 << (n)) - 1)) -#define MID(k, m, n) LAST((k) >> (m), ((n) - (m))) +#define GET_MID_BITS(k, m, n) GET_LS_BITS((k) >> (m), ((n) - (m))) #endif /* DEFINITIONS_H_INCLUDED */ diff --git a/src/utils/utils.cc b/src/utils/utils.cc index 52be177..dfeb2b3 100644 --- a/src/utils/utils.cc +++ b/src/utils/utils.cc @@ -4,8 +4,8 @@ void get_bit_fields(int address, int *tag, int *index, int *offset) { *tag = - MID(address, LINE_SPEC + L1_CACHE_SPEC, + GET_MID_BITS(address, LINE_SPEC + L1_CACHE_SPEC, MEM_SPEC + LINE_SPEC + L1_CACHE_SPEC); - *index = MID(address, LINE_SPEC, L1_CACHE_SPEC + LINE_SPEC); - *offset = LAST(address, LINE_SPEC); + *index = GET_MID_BITS(address, LINE_SPEC, L1_CACHE_SPEC + LINE_SPEC); + *offset = GET_LS_BITS(address, LINE_SPEC); } -- cgit v1.2.3 From 5cf5ebce233cc49cc04ac8c7713e12e87bab7798 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 18:28:08 -0400 Subject: Move do_write to dram.h, is_blocked flag --- inc/cache.h | 7 +++++++ inc/dram.h | 8 ++++++++ inc/storage.h | 14 +++++++++----- src/storage/cache.cc | 7 ++++++- src/storage/dram.cc | 8 ++++++++ src/storage/storage.cc | 10 +--------- 6 files changed, 39 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/inc/cache.h b/inc/cache.h index 4e4b48d..a317f5d 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -27,6 +27,13 @@ class Cache : public Storage std::array &data) override; private: + /** + * Fetches `address` from a lower level of storage if it is not already + * present. If it is not, temporarily sets the is_blocked attribute of this + * cache level to true. + * @param the address that must be present in cache. + */ + void fetch_resource(int address); /** * An array of paired bits. * If the least significant bit of an element is set, the corresponding diff --git a/inc/dram.h b/inc/dram.h index 1061d6b..20221b7 100644 --- a/inc/dram.h +++ b/inc/dram.h @@ -19,7 +19,15 @@ class Dram : public Storage Response read(Accessor accessor, int address, std::array& data) override; private: + /** + * Helper for `write`. + */ + void do_write(signed int, int); + /** + * Helper for `read`. + */ void do_read(std::array& data_line, int address); }; #endif /* DRAM_H_INCLUDED */ + diff --git a/inc/storage.h b/inc/storage.h index 1fb41b0..9707041 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -32,7 +32,10 @@ class Storage * @return a status code reflecting the state of the request, and the * data being returned. */ - virtual Response read(Accessor accessor, int address, std::array& data) = 0; + virtual Response read( + Accessor accessor, + int address, + std::array &data) = 0; /** * Sidedoor view of `lines` of memory starting at `base`. * @param The base line to start getting memory from. @@ -47,10 +50,6 @@ class Storage void resolve(); protected: - /** - * Helper for `write`. - */ - void do_write(signed int, int); /** * The data currently stored in this level of storage. */ @@ -73,6 +72,11 @@ class Storage * The number of cycles until the current request is completed. */ int wait_time; + /** + * A flag indicating whether this level of storage is currently blocked by a + * lower level. + */ + int is_blocked; }; #endif /* STORAGE_H_INCLUDED */ diff --git a/src/storage/cache.cc b/src/storage/cache.cc index cf954b0..e0eaf58 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -24,8 +24,9 @@ Response Cache::write(Accessor accessor, signed int data, int address) this->requester = accessor; if (this->requester == accessor) { + fetch_resource(address); if (this->wait_time == 0) { - this->do_write(data, address); + // this->do_write(data, address); r = OK; } } @@ -34,3 +35,7 @@ Response Cache::write(Accessor accessor, signed int data, int address) } Response Cache::read(Accessor accessor, int address, std::array& data) { return WAIT; } + +void Cache::fetch_resource(int address) { + +} diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 0db4c35..e3f3c9a 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -15,6 +15,14 @@ Dram::Dram(int lines, int delay) Dram::~Dram() { delete this->data; } +void Dram::do_write(signed data, int address) +{ + int line = address / LINE_SIZE; + int word = address % LINE_SIZE; + + this->data->at(line).at(word) = data; +} + Response Dram::write(Accessor accessor, signed int data, int address) { Response r = WAIT; diff --git a/src/storage/storage.cc b/src/storage/storage.cc index e3067a2..f382b3e 100644 --- a/src/storage/storage.cc +++ b/src/storage/storage.cc @@ -13,20 +13,12 @@ Storage::view(int base, int lines) return ret; } -void Storage::do_write(signed data, int address) -{ - int line = address / LINE_SIZE; - int word = address % LINE_SIZE; - - this->data->at(line).at(word) = data; -} - void Storage::resolve() { if (this->wait_time == 0) { this->requester = IDLE; this->wait_time = delay; - } else if (this->requester != IDLE) { + } else if (this->requester != IDLE && !this->is_blocked) { --this->wait_time; } } -- cgit v1.2.3 From 9bd18b0499d5096bc91b09a2d26e700ca1560de4 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 20:15:45 -0400 Subject: Untested implementation for loading absent data into cache --- inc/cache.h | 12 ++++++------ inc/storage.h | 6 +++--- src/storage/cache.cc | 38 ++++++++++++++++++++++++++++++++------ src/storage/dram.cc | 11 +++++++---- src/storage/storage.cc | 2 +- 5 files changed, 49 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/inc/cache.h b/inc/cache.h index a317f5d..c8c9736 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -30,17 +30,17 @@ class Cache : public Storage /** * Fetches `address` from a lower level of storage if it is not already * present. If it is not, temporarily sets the is_blocked attribute of this - * cache level to true. + * cache level to true, and the victim line is chosen/written back. * @param the address that must be present in cache. */ void fetch_resource(int address); /** - * An array of paired bits. - * If the least significant bit of an element is set, the corresponding - * element in `data` is invalid. If the most significant bit of an element - * is set, the corresponding element in `data` is dirty. + * An array of metadata about elements in `data`. + * If the first value of an element is negative, the corresponding + * element in `data` is invalid. If the most second value of an element + * is nonzero, the corresponding element in `data` is dirty. */ - std::array, L1_CACHE_SIZE> stat; + std::array, L1_CACHE_SIZE> meta; }; #endif /* CACHE_H_INCLUDED */ diff --git a/inc/storage.h b/inc/storage.h index 9707041..793b982 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -73,10 +73,10 @@ class Storage */ int wait_time; /** - * A flag indicating whether this level of storage is currently blocked by a - * lower level. + * A flag indicating whether this level of storage is currently waiting for + * a lower level. */ - int is_blocked; + int is_waiting; }; #endif /* STORAGE_H_INCLUDED */ diff --git a/src/storage/cache.cc b/src/storage/cache.cc index e0eaf58..ec14ce6 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -1,6 +1,7 @@ #include "cache.h" #include "definitions.h" #include "response.h" +#include "utils.h" #include Cache::Cache(int lines, Storage *lower, int delay) @@ -9,8 +10,7 @@ Cache::Cache(int lines, Storage *lower, int delay) this->data->resize(L1_CACHE_SIZE); this->lower = lower; this->delay = delay; - for (int i = 0; i < L1_CACHE_SIZE; ++i) - this->stat[i] = 0b01; + this->meta.fill({-1}); } Cache::~Cache() { delete this->data; } @@ -25,8 +25,9 @@ Response Cache::write(Accessor accessor, signed int data, int address) if (this->requester == accessor) { fetch_resource(address); - if (this->wait_time == 0) { - // this->do_write(data, address); + if (this->is_waiting == true) + r = BLOCKED; + else if (this->wait_time == 0) { r = OK; } } @@ -34,8 +35,33 @@ Response Cache::write(Accessor accessor, signed int data, int address) return r; } -Response Cache::read(Accessor accessor, int address, std::array& data) { return WAIT; } +Response Cache::read( + Accessor accessor, int address, std::array &data) +{ + return WAIT; +} + +void Cache::fetch_resource(int expected) +{ + Response r = OK; + int etag, index, atag; + std::array actual; + std::array meta; -void Cache::fetch_resource(int address) { + get_bit_fields(expected, &etag, &index, nullptr); + meta = this->meta.at(index); + + if (atag != etag) { + // address not in cache + if (this->meta[index][0]) { + // occupant is dirty + // TODO + r = WAIT; + } else { + actual = this->data->at(index); + r = this->lower->read(L1CACHE, expected, actual); + } + } + this->is_waiting = (r == OK) ? false : true; } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index e3f3c9a..23dedc0 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -46,12 +46,15 @@ Response Dram::write(Accessor accessor, signed int data, int address) return r; } -void Dram::do_read(std::array& data_line, int address){ +void Dram::do_read(std::array &data_line, int address) +{ int line = address / LINE_SIZE; data_line = this->data->at(line); } -Response Dram::read(Accessor accessor, int address, std::array& data) { +Response Dram::read( + Accessor accessor, int address, std::array &data) +{ Response r = WAIT; if (this->requester == IDLE) this->requester = accessor; @@ -61,5 +64,5 @@ Response Dram::read(Accessor accessor, int address, std::arraywait_time == 0) { this->requester = IDLE; this->wait_time = delay; - } else if (this->requester != IDLE && !this->is_blocked) { + } else if (this->requester != IDLE && !this->is_waiting) { --this->wait_time; } } -- cgit v1.2.3 From 4dc12d82699520bdc6875e5177ae8a6a2c2dea04 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 20:55:45 -0400 Subject: initialize wait_time in dram to resolve undefined behavior --- src/storage/dram.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 23dedc0..9dab4ed 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -8,9 +8,10 @@ Dram::Dram(int lines, int delay) this->data = new std::vector>; this->data->resize(lines); this->delay = delay; - this->wait_time = this->delay; + this->is_waiting = false; this->lower = nullptr; this->requester = IDLE; + this->wait_time = this->delay; } Dram::~Dram() { delete this->data; } -- cgit v1.2.3 From 4676d633edaea37b5661e4f91742b42fcf5b7881 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 20:56:00 -0400 Subject: cache store single test --- inc/cache.h | 3 +-- src/storage/cache.cc | 13 +++++++++---- tests/cache.cc | 35 +++++++++++++++++++++++++++++++++-- 3 files changed, 43 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/inc/cache.h b/inc/cache.h index c8c9736..e8b7030 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -3,7 +3,6 @@ #include "definitions.h" #include "storage.h" #include -#include class Cache : public Storage { @@ -17,7 +16,7 @@ class Cache : public Storage * @param The number of clock cycles each access takes. * @return A new cache object. */ - Cache(int lines, Storage *lower, int delay); + Cache(Storage *lower, int delay); ~Cache(); Response write(Accessor accessor, signed int data, int address) override; diff --git a/src/storage/cache.cc b/src/storage/cache.cc index ec14ce6..f1ae238 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -4,7 +4,7 @@ #include "utils.h" #include -Cache::Cache(int lines, Storage *lower, int delay) +Cache::Cache(Storage *lower, int delay) { this->data = new std::vector>; this->data->resize(L1_CACHE_SIZE); @@ -28,6 +28,10 @@ Response Cache::write(Accessor accessor, signed int data, int address) if (this->is_waiting == true) r = BLOCKED; else if (this->wait_time == 0) { + int tag, index, offset; + get_bit_fields(address, &tag, &index, &offset); + this->data->at(index).at(offset) = data; + r = OK; } } @@ -44,22 +48,23 @@ Response Cache::read( void Cache::fetch_resource(int expected) { Response r = OK; - int etag, index, atag; + int etag, index, eoffset, atag; std::array actual; std::array meta; - get_bit_fields(expected, &etag, &index, nullptr); + get_bit_fields(expected, &etag, &index, &eoffset); meta = this->meta.at(index); if (atag != etag) { // address not in cache - if (this->meta[index][0]) { + if (this->meta[index][0] >= 0) { // occupant is dirty // TODO r = WAIT; } else { actual = this->data->at(index); r = this->lower->read(L1CACHE, expected, actual); + // clear dirty bit and set tag? } } diff --git a/tests/cache.cc b/tests/cache.cc index 3c1fba6..55592ae 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -1,12 +1,43 @@ #include "cache.h" #include "definitions.h" +#include "dram.h" #include -TEST_CASE("Constructor singleton dram", "[cache]") +TEST_CASE("Constructor singleton cache", "[cache]") { - Cache *c = new Cache(1, nullptr, LINE_SIZE); + Cache *c = new Cache(nullptr, 0); std::array expected = {0, 0, 0, 0}; std::array actual = c->view(0, 1)[0]; REQUIRE(expected == actual); delete c; } + +// TEST_CASE("no delay stores instantly", "[cache]") +// { +// int delay = 0; +// Dram *d = new Dram(MEM_SIZE, delay); +// Cache *c = new Cache(d, delay); +// std::array expected = {0, 0, 0, 0}; +// std::array actual = d->view(0, 1)[0]; +// CHECK(expected == actual); + +// signed int w = 0x11223344; + +// Response r; + +// r = c->write(MEM, w, 0x0000000000000); +// CHECK(r == OK); +// d->resolve(); +// c->resolve(); + +// expected.at(0) = w; +// actual = c->view(0, 1)[0]; +// REQUIRE(expected == actual); + +// actual = d->view(0, 1)[0]; +// // we do NOT write back now! +// REQUIRE(expected != actual); + +// delete d; +// delete c; +// } -- cgit v1.2.3 From 95d90e454beca2e467613d0c0fbb035b02eada23 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 21:39:07 -0400 Subject: Cache object issues with uninitialized fields, another cache test --- src/storage/cache.cc | 19 +++++++++------- tests/cache.cc | 63 +++++++++++++++++++++++++++++++++++++++++++--------- tests/dram.cc | 2 -- 3 files changed, 64 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/src/storage/cache.cc b/src/storage/cache.cc index f1ae238..52f13b9 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -8,9 +8,12 @@ Cache::Cache(Storage *lower, int delay) { this->data = new std::vector>; this->data->resize(L1_CACHE_SIZE); - this->lower = lower; this->delay = delay; - this->meta.fill({-1}); + this->is_waiting = false; + this->lower = lower; + this->meta.fill({-1, -1}); + this->requester = IDLE; + this->wait_time = this->delay; } Cache::~Cache() { delete this->data; } @@ -25,13 +28,12 @@ Response Cache::write(Accessor accessor, signed int data, int address) if (this->requester == accessor) { fetch_resource(address); - if (this->is_waiting == true) + if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { int tag, index, offset; get_bit_fields(address, &tag, &index, &offset); this->data->at(index).at(offset) = data; - r = OK; } } @@ -48,16 +50,16 @@ Response Cache::read( void Cache::fetch_resource(int expected) { Response r = OK; - int etag, index, eoffset, atag; + int tag, index, offset; std::array actual; std::array meta; - get_bit_fields(expected, &etag, &index, &eoffset); + get_bit_fields(expected, &tag, &index, &offset); meta = this->meta.at(index); - if (atag != etag) { + if (this->meta[index][0] != tag) { // address not in cache - if (this->meta[index][0] >= 0) { + if (this->meta[index][1] >= 0) { // occupant is dirty // TODO r = WAIT; @@ -65,6 +67,7 @@ void Cache::fetch_resource(int expected) actual = this->data->at(index); r = this->lower->read(L1CACHE, expected, actual); // clear dirty bit and set tag? + } } diff --git a/tests/cache.cc b/tests/cache.cc index 55592ae..9e6521a 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -12,31 +12,74 @@ TEST_CASE("Constructor singleton cache", "[cache]") delete c; } -// TEST_CASE("no delay stores instantly", "[cache]") +TEST_CASE("no delay stores instantly", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + Response r; + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + d->resolve(); + c->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +// TEST_CASE("cache takes \"forever\"", "[cache]") // { // int delay = 0; // Dram *d = new Dram(MEM_SIZE, delay); -// Cache *c = new Cache(d, delay); +// Cache *c = new Cache(d, delay + 2); // std::array expected = {0, 0, 0, 0}; // std::array actual = d->view(0, 1)[0]; // CHECK(expected == actual); // signed int w = 0x11223344; +// int i; // Response r; - -// r = c->write(MEM, w, 0x0000000000000); +// for (i = 0; i < delay + 2; ++i) { +// r = c->write(MEM, w, 0x0000000000000); +// CHECK(r == WAIT); + +// // keep dram busy +// r = d->write(MEM, w, 0x0000000000101); +// CHECK(r == OK); + +// actual = c->view(0, 1)[0]; +// REQUIRE(expected == actual); +// c->resolve(); +// d->resolve(); +// } + +// r = c->write(MEM, w, 0x0000000000000); // CHECK(r == OK); // d->resolve(); -// c->resolve(); - -// expected.at(0) = w; -// actual = c->view(0, 1)[0]; -// REQUIRE(expected == actual); // actual = d->view(0, 1)[0]; // // we do NOT write back now! -// REQUIRE(expected != actual); +// REQUIRE(expected == actual); + +// expected.at(1) = w; +// actual = c->view(0, 1)[0]; +// REQUIRE(expected == actual); // delete d; // delete c; diff --git a/tests/dram.cc b/tests/dram.cc index 95ef90a..27fc24f 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -85,8 +85,6 @@ TEST_CASE( CHECK(r == WAIT); actual = d->view(0, 1)[0]; - CHECK(r == WAIT); - REQUIRE(expected == actual); d->resolve(); } -- cgit v1.2.3 From 2669ab2cfccd9b0b3954e6a68af3de67bd951938 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 23:49:29 -0400 Subject: Properly set cache metadata when a value is loaded --- src/storage/cache.cc | 15 +++-- src/storage/dram.cc | 3 + tests/cache.cc | 169 ++++++++++++++++++++++++++++++++++++++------------- 3 files changed, 139 insertions(+), 48 deletions(-) (limited to 'src') diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 52f13b9..2031367 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -34,6 +34,7 @@ Response Cache::write(Accessor accessor, signed int data, int address) int tag, index, offset; get_bit_fields(address, &tag, &index, &offset); this->data->at(index).at(offset) = data; + this->meta[index].at(1) = 1; r = OK; } } @@ -52,22 +53,24 @@ void Cache::fetch_resource(int expected) Response r = OK; int tag, index, offset; std::array actual; - std::array meta; + std::array *meta; get_bit_fields(expected, &tag, &index, &offset); - meta = this->meta.at(index); + meta = &this->meta.at(index); - if (this->meta[index][0] != tag) { + if (meta->at(0) != tag) { // address not in cache - if (this->meta[index][1] >= 0) { + if (meta->at(1) >= 0) { // occupant is dirty // TODO r = WAIT; } else { actual = this->data->at(index); r = this->lower->read(L1CACHE, expected, actual); - // clear dirty bit and set tag? - + if (r == OK) { + meta->at(0) = tag; + meta->at(1) = -1; + } } } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 9dab4ed..441f10b 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -57,13 +57,16 @@ Response Dram::read( Accessor accessor, int address, std::array &data) { Response r = WAIT; + if (this->requester == IDLE) this->requester = accessor; + if (this->requester == accessor) { if (this->wait_time == 0) { this->do_read(data, address); r = OK; } } + return r; } diff --git a/tests/cache.cc b/tests/cache.cc index 9e6521a..64819b6 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -42,45 +42,130 @@ TEST_CASE("no delay stores instantly", "[cache]") delete c; } -// TEST_CASE("cache takes \"forever\"", "[cache]") -// { -// int delay = 0; -// Dram *d = new Dram(MEM_SIZE, delay); -// Cache *c = new Cache(d, delay + 2); -// std::array expected = {0, 0, 0, 0}; -// std::array actual = d->view(0, 1)[0]; -// CHECK(expected == actual); - -// signed int w = 0x11223344; - -// int i; -// Response r; -// for (i = 0; i < delay + 2; ++i) { -// r = c->write(MEM, w, 0x0000000000000); -// CHECK(r == WAIT); - -// // keep dram busy -// r = d->write(MEM, w, 0x0000000000101); -// CHECK(r == OK); - -// actual = c->view(0, 1)[0]; -// REQUIRE(expected == actual); -// c->resolve(); -// d->resolve(); -// } - -// r = c->write(MEM, w, 0x0000000000000); -// CHECK(r == OK); -// d->resolve(); - -// actual = d->view(0, 1)[0]; -// // we do NOT write back now! -// REQUIRE(expected == actual); - -// expected.at(1) = w; -// actual = c->view(0, 1)[0]; -// REQUIRE(expected == actual); - -// delete d; -// delete c; -// } +TEST_CASE("cache takes \"forever\"", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay); + Cache *c = new Cache(d, delay + 2); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == WAIT); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +TEST_CASE("dram takes \"forever\"", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay + 2); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == BLOCKED); // BLOCKED + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +TEST_CASE("dram and cache take \"forever\"", "[cache]") +{ + int delay = 2; + Dram *d = new Dram(MEM_SIZE, delay + 2); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == BLOCKED); // BLOCKED + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + for (i = 0; i < delay; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == WAIT); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + c->resolve(); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} -- cgit v1.2.3