From 28a2788e2c59357d9269e558b0bd45db3241c42d Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 12 Apr 2025 00:44:29 -0400 Subject: Rewrite utils functions as macros --- tests/utils.cc | 65 ---------------------------------------------------------- 1 file changed, 65 deletions(-) delete mode 100644 tests/utils.cc (limited to 'tests') diff --git a/tests/utils.cc b/tests/utils.cc deleted file mode 100644 index 2e0e934..0000000 --- a/tests/utils.cc +++ /dev/null @@ -1,65 +0,0 @@ -#include "utils.h" -#include "definitions.h" -#include - -TEST_CASE("Parse arbitrary fields # one", "[utils]") -{ - int tag, index, offset; - int address = 0b0001010101; - get_cache_fields(address, &tag, &index, &offset); - CHECK(tag == 0b000); - CHECK(index == 0b10101); - CHECK(offset == 0b01); -} - -TEST_CASE("Parse arbitrary fields # two", "[utils]") -{ - int tag, index, offset; - int address = 0b0100111011; - get_cache_fields(address, &tag, &index, &offset); - CHECK(tag == 0b010); - CHECK(index == 0b01110); - CHECK(offset == 0b11); -} - -TEST_CASE("wrap address outside upper bound", "[utils]") -{ - int address = MEM_WORDS + 25; - int wrapped = wrap_address(address); - REQUIRE(wrapped == 25); -} - -TEST_CASE("wrap address inside upper bound", "[utils]") -{ - int address = MEM_WORDS - 25; - int wrapped = wrap_address(address); - REQUIRE(wrapped == MEM_WORDS - 25); -} - -TEST_CASE("wrap address at upper bound", "[utils]") -{ - int address = MEM_WORDS; - int wrapped = wrap_address(address); - REQUIRE(wrapped == 0); -} - -TEST_CASE("wrap address lower than 0 with magnitude lesser than mem size", "[utils]") -{ - int address = -10; - int wrapped = wrap_address(address); - REQUIRE(wrapped == MEM_WORDS - 10); -} - -TEST_CASE("wrap address lower than 0 but with magnitude greater than mem size", "[utils]") -{ - int address = -(MEM_WORDS + 10); - int wrapped = wrap_address(address); - REQUIRE(wrapped == MEM_WORDS - 10); -} - -TEST_CASE("wrap address at 0", "[utils]") -{ - int address = 0; - int wrapped = wrap_address(address); - REQUIRE(wrapped == 0); -} -- cgit v1.2.3 From b91eb002d4e6b2dc0c51b03df57c5089659ac669 Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 12 Apr 2025 01:36:59 -0400 Subject: Add C11 test class header as base cache fixture class --- CMakeLists.txt | 2 +- inc/definitions.h | 4 +- tests/c11.h | 47 +++++++++++++++ tests/cache.cc | 167 ----------------------------------------------------- tests/cache_1_1.cc | 111 +++++++++++++++++++++++++++++++++++ tests/dram.cc | 38 ++++++------ 6 files changed, 181 insertions(+), 188 deletions(-) create mode 100644 tests/c11.h delete mode 100644 tests/cache.cc create mode 100644 tests/cache_1_1.cc (limited to 'tests') diff --git a/CMakeLists.txt b/CMakeLists.txt index 661e45c..558f214 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -27,7 +27,7 @@ if(RAM_TESTS) # test executable add_executable(tests ${SRCS} ${TESTS}) - target_include_directories(tests PUBLIC ${PROJECT_SOURCE_DIR}/inc) + target_include_directories(tests PRIVATE ${PROJECT_SOURCE_DIR}/inc ${PROJECT_SOURCE_DIR}/inc) target_link_libraries(tests PRIVATE Catch2::Catch2WithMain PRIVATE) # test discovery diff --git a/inc/definitions.h b/inc/definitions.h index 94414a4..113c6e4 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -73,14 +73,14 @@ #define GET_FIELDS(a, t, i, o) \ *(t) = GET_MID_BITS(a, L1_CACHE_LINE_SPEC + LINE_SPEC, MEM_WORD_SPEC); \ *(i) = GET_MID_BITS(a, LINE_SPEC, L1_CACHE_LINE_SPEC + LINE_SPEC); \ - *(o) = GET_LS_BITS(a, LINE_SPEC); \ + *(o) = GET_LS_BITS(a, LINE_SPEC) /** * Ensures address is within the current memory size using a clean wrap. * @param an address */ #define WRAP_ADDRESS(a) \ - ((a < 0) ? ((a % MEM_WORDS) + MEM_WORDS) % MEM_WORDS : a % MEM_WORDS) \ + ((a < 0) ? ((a % MEM_WORDS) + MEM_WORDS) % MEM_WORDS : a % MEM_WORDS) // clang-format on #endif /* DEFINITIONS_H_INCLUDED */ diff --git a/tests/c11.h b/tests/c11.h new file mode 100644 index 0000000..eb59cc0 --- /dev/null +++ b/tests/c11.h @@ -0,0 +1,47 @@ +#include "cache.h" +#include "dram.h" +#include "storage.h" +#include +#include +#include +#include + +class C11 +{ + public: + C11() : m_delay(4), c_delay(2), mem(new int), fetch(new int) + { + this->c = new Cache(new Dram(this->m_delay), this->c_delay); + this->expected = {0, 0, 0, 0}; + this->actual = this->c->view(0, 1)[0]; + } + + ~C11() + { + delete this->c; + delete this->mem; + delete this->fetch; + } + + void + wait_then_do(int delay, std::function f) + { + for (int i = 0; i < delay; ++i) { + int r = f(); + + // check response + CHECK(!r); + // check for early modifications + actual = c->view(0, 1)[0]; + REQUIRE(this->expected == this->actual); + } + } + + int m_delay; + int c_delay; + Cache *c; + int *mem; + int *fetch; + std::array expected; + std::array actual; +}; diff --git a/tests/cache.cc b/tests/cache.cc deleted file mode 100644 index 313f93f..0000000 --- a/tests/cache.cc +++ /dev/null @@ -1,167 +0,0 @@ -#include "cache.h" -#include "dram.h" -#include - -class CacheFixture -{ - public: - CacheFixture() - { - this->m_delay = 4; - this->c_delay = 2; - this->d = new Dram(this->m_delay); - this->c = new Cache(this->d, this->c_delay); - this->mem = new int; - this->fetch = new int; - this->expected = {0, 0, 0, 0}; - this->actual = this->c->view(0, 1)[0]; - } - - ~CacheFixture() - { - delete this->c; - delete this->mem; - delete this->fetch; - } - - /** - * An operation that is done a lot. - */ - void - wait_for_storage(int delay, int expected, std::function f) - { - for (int i = 0; i < delay; ++i) { - int r = f(); - - // check response - CHECK(r == expected); - // check for early modifications - actual = c->view(0, 1)[0]; - REQUIRE(this->expected == this->actual); - } - } - - int m_delay; - int c_delay; - Cache *c; - Dram *d; - int *mem; - int *fetch; - std::array expected; - std::array actual; -}; - -TEST_CASE_METHOD(CacheFixture, "store 0th element in DELAY cycles", "[dram]") -{ - int r; - signed int w; - CHECK(expected == actual); - - w = 0x11223344; - // delay + 1 due to internal logic, when mem - // finishes handle_miss still returns 'blocked' - this->wait_for_storage(this->m_delay + this->c_delay + 1, 0, [this, w]() { - return this->c->write_word(this->mem, w, 0b0); - }); - - r = c->write_word(this->mem, w, 0b0); - CHECK(r); - - actual = this->d->view(0, 1)[0]; - // we do NOT write back now! - REQUIRE(expected == actual); - - expected.at(0) = w; - actual = c->view(0, 1)[0]; - REQUIRE(expected == actual); -} - -TEST_CASE_METHOD(CacheFixture, "store 0th, 1st element in DELAY cycles, with conflict", "[cache]") -{ - signed int w; - int r, i; - CHECK(expected == actual); - - w = 0x11223344; - // delay + 1 due to internal logic, when mem - // finishes handle_miss still returns 'blocked' - for (i = 0; i < this->m_delay + this->c_delay + 1; ++i) { - r = c->write_word(this->mem, w, 0b0); - CHECK(!r); - r = c->write_word(this->fetch, w, 0b1); - CHECK(!r); - - // check for early modifications - actual = c->view(0, 1)[0]; - REQUIRE(this->expected == this->actual); - } - - r = c->write_word(this->mem, w, 0b0); - CHECK(r); - - actual = d->view(0, 1)[0]; - // we do NOT write back now! - REQUIRE(expected == actual); - - expected.at(0) = w; - actual = c->view(0, 1)[0]; - REQUIRE(expected == actual); - - // this should have been loaded already! - this->wait_for_storage( - this->c_delay, 0, [this, w]() { return this->c->write_word(this->fetch, w, 0b1); }); - - r = c->write_word(this->fetch, w, 0b1); - CHECK(r); - - expected.at(1) = w; - actual = c->view(0, 1)[0]; - REQUIRE(expected == actual); -} - -TEST_CASE_METHOD( - CacheFixture, "store 0th, 1st element different tags, in DELAY cycles, no conflict", "[cache]") -{ - int r; - signed int w; - CHECK(expected == actual); - - w = 0x11223344; - // delay + 1 due to internal logic, when mem - // finishes handle_miss still returns 'blocked' - this->wait_for_storage(this->m_delay + this->c_delay + 1, 0, [this, w]() { - return this->c->write_word(this->mem, w, 0b0); - }); - - r = c->write_word(this->mem, w, 0b0); - CHECK(r); - - expected.at(0) = w; - actual = c->view(0, 1)[0]; - REQUIRE(expected == actual); - - // write back to memory - // fetch new address (don't run the completion cycle yet) - this->wait_for_storage(this->m_delay + this->m_delay + 1, 0, [this, w]() { - return this->c->write_word(this->fetch, w, 0b10000001); - }); - - // after the fetch, this cache line should be empty - this->c->write_word(this->fetch, w, 0b10000001); - CHECK(r); - - expected.at(0) = 0; - actual = c->view(0, 1)[0]; - CHECK(expected == actual); - - this->wait_for_storage( - this->c_delay, 0, [this, w]() { return this->c->write_word(this->fetch, w, 0b10000001); }); - - r = c->write_word(this->fetch, w, 0b10000001); - CHECK(r); - - expected.at(0) = 0; - expected.at(1) = w; - actual = c->view(0, 1)[0]; - REQUIRE(expected == actual); -} diff --git a/tests/cache_1_1.cc b/tests/cache_1_1.cc new file mode 100644 index 0000000..e3677a4 --- /dev/null +++ b/tests/cache_1_1.cc @@ -0,0 +1,111 @@ +#include "c11.h" +#include "cache.h" +#include "dram.h" +#include + +TEST_CASE_METHOD(C11, "store 0th element in DELAY cycles", "[dram]") +{ + int r; + signed int w; + CHECK(expected == actual); + + w = 0x11223344; + // delay + 1 due to internal logic, when mem + // finishes handle_miss still returns 'blocked' + this->wait_then_do(this->m_delay + this->c_delay + 1, [this, w]() { + return this->c->write_word(this->mem, w, 0b0); + }); + + r = c->write_word(this->mem, w, 0b0); + CHECK(r); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); +} + +TEST_CASE_METHOD(C11, "store 0th, 1st element in DELAY cycles, with conflict", "[cache]") +{ + signed int w; + int r, i; + CHECK(expected == actual); + + w = 0x11223344; + // delay + 1 due to internal logic, when mem + // finishes handle_miss still returns 'blocked' + for (i = 0; i < this->m_delay + this->c_delay + 1; ++i) { + r = c->write_word(this->mem, w, 0b0); + CHECK(!r); + r = c->write_word(this->fetch, w, 0b1); + CHECK(!r); + + // check for early modifications + actual = c->view(0, 1)[0]; + REQUIRE(this->expected == this->actual); + } + + r = c->write_word(this->mem, w, 0b0); + CHECK(r); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + // this should have been loaded already! + this->wait_then_do( + this->c_delay, [this, w]() { return this->c->write_word(this->fetch, w, 0b1); }); + + r = c->write_word(this->fetch, w, 0b1); + CHECK(r); + + expected.at(1) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); +} + +TEST_CASE_METHOD( + C11, "store 0th, 1st element different tags, in DELAY cycles, no conflict", "[cache]") +{ + int r; + signed int w; + CHECK(expected == actual); + + w = 0x11223344; + // delay + 1 due to internal logic, when mem + // finishes handle_miss still returns 'blocked' + this->wait_then_do(this->m_delay + this->c_delay + 1, [this, w]() { + return this->c->write_word(this->mem, w, 0b0); + }); + + r = c->write_word(this->mem, w, 0b0); + CHECK(r); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + // write back to memory + // fetch new address (don't run the completion cycle yet) + this->wait_then_do(this->m_delay + this->m_delay + 1, [this, w]() { + return this->c->write_word(this->fetch, w, 0b10000001); + }); + + // after the fetch, this cache line should be empty + this->c->write_word(this->fetch, w, 0b10000001); + CHECK(r); + + expected.at(0) = 0; + actual = c->view(0, 1)[0]; + CHECK(expected == actual); + + this->wait_then_do( + this->c_delay, [this, w]() { return this->c->write_word(this->fetch, w, 0b10000001); }); + + r = c->write_word(this->fetch, w, 0b10000001); + CHECK(r); + + expected.at(0) = 0; + expected.at(1) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); +} diff --git a/tests/dram.cc b/tests/dram.cc index 086ca4a..06a7720 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -2,10 +2,10 @@ #include #include -class DramFixture +class D { public: - DramFixture() + D() { this->delay = 3; this->d = new Dram(this->delay); @@ -15,7 +15,7 @@ class DramFixture this->actual = this->d->view(0, 1)[0]; } - ~DramFixture() + ~D() { delete this->d; delete this->mem; @@ -44,14 +44,15 @@ class DramFixture std::array actual; }; -TEST_CASE_METHOD(DramFixture, "store 0th element in DELAY cycles", "[dram]") +TEST_CASE_METHOD(D, "store 0th element in DELAY cycles", "[dram]") { int r; signed int w; CHECK(expected == actual); w = 0x11223344; - this->wait_for_storage(this->delay, [this, w]() { return this->d->write_word(this->mem, w, 0x0); }); + this->wait_for_storage( + this->delay, [this, w]() { return this->d->write_word(this->mem, w, 0x0); }); r = this->d->write_word(this->mem, w, 0x0); @@ -61,14 +62,15 @@ TEST_CASE_METHOD(DramFixture, "store 0th element in DELAY cycles", "[dram]") REQUIRE(expected == actual); } -TEST_CASE_METHOD(DramFixture, "store 0th, 1st element in DELAY cycles, no conflict", "[dram]") +TEST_CASE_METHOD(D, "store 0th, 1st element in DELAY cycles, no conflict", "[dram]") { int r; signed int w; CHECK(expected == actual); w = 0x11223344; - this->wait_for_storage(this->delay, [this, w]() { return this->d->write_word(this->mem, w, 0x0); }); + this->wait_for_storage( + this->delay, [this, w]() { return this->d->write_word(this->mem, w, 0x0); }); r = d->write_word(this->mem, w, 0x0); REQUIRE(r); @@ -77,7 +79,8 @@ TEST_CASE_METHOD(DramFixture, "store 0th, 1st element in DELAY cycles, no confli actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - this->wait_for_storage(this->delay, [this, w]() { return this->d->write_word(this->fetch, w, 0x1); }); + this->wait_for_storage( + this->delay, [this, w]() { return this->d->write_word(this->fetch, w, 0x1); }); r = d->write_word(this->fetch, w, 0x1); CHECK(r); @@ -87,7 +90,7 @@ TEST_CASE_METHOD(DramFixture, "store 0th, 1st element in DELAY cycles, no confli REQUIRE(expected == actual); } -TEST_CASE_METHOD(DramFixture, "store 0th element in DELAY cycles with conflict", "[dram]") +TEST_CASE_METHOD(D, "store 0th element in DELAY cycles with conflict", "[dram]") { int r, i; signed int w; @@ -112,7 +115,8 @@ TEST_CASE_METHOD(DramFixture, "store 0th element in DELAY cycles with conflict", actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - this->wait_for_storage(this->delay, [this, w]() { return this->d->write_word(this->fetch, w, 0x1); }); + this->wait_for_storage( + this->delay, [this, w]() { return this->d->write_word(this->fetch, w, 0x1); }); r = d->write_word(this->fetch, w, 0x1); CHECK(r); @@ -122,7 +126,7 @@ TEST_CASE_METHOD(DramFixture, "store 0th element in DELAY cycles with conflict", REQUIRE(expected == actual); } -TEST_CASE_METHOD(DramFixture, "store line in DELAY cycles", "[dram]") +TEST_CASE_METHOD(D, "store line in DELAY cycles", "[dram]") { int r; signed int w; @@ -142,7 +146,7 @@ TEST_CASE_METHOD(DramFixture, "store line in DELAY cycles", "[dram]") REQUIRE(expected == actual); } -TEST_CASE_METHOD(DramFixture, "store line in DELAY cycles no conflict", "[dram]") +TEST_CASE_METHOD(D, "store line in DELAY cycles no conflict", "[dram]") { int r; signed int w; @@ -173,7 +177,7 @@ TEST_CASE_METHOD(DramFixture, "store line in DELAY cycles no conflict", "[dram]" REQUIRE(expected == actual); } -TEST_CASE_METHOD(DramFixture, "store line in DELAY cycles with conflict", "[dram]") +TEST_CASE_METHOD(D, "store line in DELAY cycles with conflict", "[dram]") { int r, i; signed int w; @@ -212,8 +216,7 @@ TEST_CASE_METHOD(DramFixture, "store line in DELAY cycles with conflict", "[dram REQUIRE(expected == actual); } -TEST_CASE_METHOD( - DramFixture, "store line in DELAY cycles, read in DELAY cycles, no conflict", "[dram]") +TEST_CASE_METHOD(D, "store line in DELAY cycles, read in DELAY cycles, no conflict", "[dram]") { int r, i, addr; signed int w; @@ -242,8 +245,7 @@ TEST_CASE_METHOD( REQUIRE(expected == actual); } -TEST_CASE_METHOD( - DramFixture, "store line in DELAY cycles, read in DELAY cycles with conflict", "[dram]") +TEST_CASE_METHOD(D, "store line in DELAY cycles, read in DELAY cycles with conflict", "[dram]") { int r, i, addr; signed int w; @@ -276,7 +278,7 @@ TEST_CASE_METHOD( } TEST_CASE_METHOD( - DramFixture, + D, "store line in DELAY cycles, read one element at a time in DELAY cycles " "with conflict", "[dram]") -- cgit v1.2.3 From ee433509972d9390a52f188e902eb74e55596822 Mon Sep 17 00:00:00 2001 From: bd Date: Mon, 14 Apr 2025 16:28:05 -0400 Subject: Allow multi-level cache by passing a size into the constructor --- inc/cache.h | 56 ++++++++++++++++++++++++++++++------------------------ inc/definitions.h | 31 ------------------------------ inc/dram.h | 9 +++++++++ src/cache.cc | 24 +++++++++-------------- src/dram.cc | 1 - tests/c11.h | 11 +++++++++-- tests/cache_2_1.cc | 21 ++++++++++++++++++++ 7 files changed, 79 insertions(+), 74 deletions(-) create mode 100644 tests/cache_2_1.cc (limited to 'tests') diff --git a/inc/cache.h b/inc/cache.h index 0f15536..325d46f 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -3,40 +3,45 @@ #include "definitions.h" #include "storage.h" #include +#include #include #include +/** + * Parse an address into a tag, index into the cache table, and a line + * offset. + * @param the address to be parsed + * @param the resulting tag + * @param the resulting index + * @param the resulting offset + */ +// clang-format off +#define GET_FIELDS(a, t, i, o) \ + *(t) = GET_MID_BITS(a, this->size + LINE_SPEC, MEM_WORD_SPEC); \ + *(i) = GET_MID_BITS(a, LINE_SPEC, this->size + LINE_SPEC); \ + *(o) = GET_LS_BITS(a, LINE_SPEC) +// clang-format on + class Cache : public Storage { public: /** - * Constructor. +nn * Constructor. * @param The number of `lines` contained in memory. The total number of * words is this number multiplied by LINE_SIZE. * @param The next lowest level in storage. Methods from this object are * called in case of a cache miss. + * @param The number of bits required to specify a line in this level of cache. * @param The number of clock cycles each access takes. * @return A new cache object. */ - Cache(Storage *lower, int delay); + Cache(Storage *lower, unsigned int size, int delay); ~Cache(); - int - write_word(void *, signed int, int) override; - int - write_line(void *, std::array, int) override; - int - read_line(void *, int, std::array &) override; - int - read_word(void *, int, signed int &) override; - - /** - * Getter for the meta attribute. - * TODO this doesn't seem like good object-oriented practice. - * @return this->meta - */ - std::array, L1_CACHE_LINES> - get_meta() const; + int write_word(void *, signed int, int) override; + int write_line(void *, std::array, int) override; + int read_line(void *, int, std::array &) override; + int read_word(void *, int, signed int &) override; private: /** @@ -47,8 +52,7 @@ class Cache : public Storage * @param the address to write to * @param the function to call when an access should be completed */ - int - process(void *id, int address, std::function request_handler); + int process(void *id, int address, std::function request_handler); /** * Returns OK if `id` is allowed to complete its request this cycle. * Handles cache misses, wait times, and setting the current id this @@ -56,8 +60,7 @@ class Cache : public Storage * @param the id asking for a resource * @return 1 if the access can be carried out this function call, 0 otherwise. */ - int - is_access_cleared(void *id, int address); + int is_access_cleared(void *id, int address); /** * Helper for is_access_cleared. * Fetches `address` from a lower level of storage if it is not already @@ -65,15 +68,18 @@ class Cache : public Storage * @param the address that must be present in cache. * @param 0 if the address is currently in cache, 1 if it is being fetched. */ - int - is_address_missing(int address); + int is_address_missing(int address); + /** + * The number of bits required to specify a line in this level of cache. + */ + unsigned int size; /** * An array of metadata about elements in `data`. * If the first value of an element is negative, the corresponding * element in `data` is invalid. If the most second value of an element * is nonzero, the corresponding element in `data` is dirty. */ - std::array, L1_CACHE_LINES> meta; + std::vector> meta; }; #endif /* CACHE_H_INCLUDED */ diff --git a/inc/definitions.h b/inc/definitions.h index 113c6e4..db43426 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -25,15 +25,6 @@ #define MEM_WORDS static_cast(pow(2, MEM_WORD_SPEC)) #define MEM_LINES static_cast(pow(2, MEM_LINE_SPEC)) -/** - * The number of bits to specify a l1 cache word - * The number of bits to specify a l1 cache line - * The total number of lines in l1 cache - */ -#define L1_CACHE_WORD_SPEC 7 -#define L1_CACHE_LINE_SPEC static_cast(L1_CACHE_WORD_SPEC - LINE_SPEC) -#define L1_CACHE_LINES static_cast(pow(2, L1_CACHE_LINE_SPEC)) - /** * The total number of cycles a memory access takes */ @@ -61,26 +52,4 @@ */ #define GET_MID_BITS(k, m, n) GET_LS_BITS((k) >> (m), ((n) - (m))) -/** - * Parse an address into a tag, index into the cache table, and a line - * offset. - * @param the address to be parsed - * @param the resulting tag - * @param the resulting index - * @param the resulting offset - */ -// clang-format off -#define GET_FIELDS(a, t, i, o) \ - *(t) = GET_MID_BITS(a, L1_CACHE_LINE_SPEC + LINE_SPEC, MEM_WORD_SPEC); \ - *(i) = GET_MID_BITS(a, LINE_SPEC, L1_CACHE_LINE_SPEC + LINE_SPEC); \ - *(o) = GET_LS_BITS(a, LINE_SPEC) - -/** - * Ensures address is within the current memory size using a clean wrap. - * @param an address - */ -#define WRAP_ADDRESS(a) \ - ((a < 0) ? ((a % MEM_WORDS) + MEM_WORDS) % MEM_WORDS : a % MEM_WORDS) -// clang-format on - #endif /* DEFINITIONS_H_INCLUDED */ diff --git a/inc/dram.h b/inc/dram.h index 140cbb1..fc46b47 100644 --- a/inc/dram.h +++ b/inc/dram.h @@ -5,6 +5,15 @@ #include #include +// clang-format off +/** + * Ensures address is within the current memory size using a clean wrap. + * @param an address + */ +#define WRAP_ADDRESS(a) \ + ((a < 0) ? ((a % MEM_WORDS) + MEM_WORDS) % MEM_WORDS : a % MEM_WORDS) +// clang-format on + class Dram : public Storage { public: diff --git a/src/cache.cc b/src/cache.cc index acbabcf..307d6d0 100644 --- a/src/cache.cc +++ b/src/cache.cc @@ -1,13 +1,17 @@ #include "cache.h" #include "definitions.h" -#include +#include #include -Cache::Cache(Storage *lower, int delay) : Storage(delay) +Cache::Cache(Storage *lower, unsigned int size, int delay) : Storage(delay) { - this->data->resize(L1_CACHE_LINES); + int true_size; + + true_size = 1 << size; + this->data->resize(true_size); + this->meta = std::vector>(true_size, {-1, -1}); + this->size = size; this->lower = lower; - this->meta.fill({-1, -1}); } Cache::~Cache() @@ -35,7 +39,6 @@ Cache::write_line(void *id, std::array data_line, int add }); } -// TODO: tests for multi level cache int Cache::read_line(void *id, int address, std::array &data_line) { @@ -103,8 +106,7 @@ Cache::is_address_missing(int expected) r = 1; if (meta->at(1) >= 0) { q = this->lower->write_line( - this, *actual, - ((index << LINE_SPEC) + (meta->at(0) << (L1_CACHE_LINE_SPEC + LINE_SPEC)))); + this, *actual, ((index << LINE_SPEC) + (meta->at(0) << (this->size + LINE_SPEC)))); if (q) { meta->at(1) = -1; } @@ -118,11 +120,3 @@ Cache::is_address_missing(int expected) return r; } - -std::array, L1_CACHE_LINES> -Cache::get_meta() const -{ - std::array, L1_CACHE_LINES> ret; - std::copy(std::begin(this->meta), std::end(this->meta), std::begin(ret)); - return ret; -} diff --git a/src/dram.cc b/src/dram.cc index 2fd8a91..18c1a3e 100644 --- a/src/dram.cc +++ b/src/dram.cc @@ -24,7 +24,6 @@ Dram::write_word(void *id, signed int data, int address) return process(id, address, [&](int line, int word) { this->data->at(line).at(word) = data; }); } -// TODO requires testing int Dram::read_line(void *id, int address, std::array &data_line) { diff --git a/tests/c11.h b/tests/c11.h index eb59cc0..6d63c77 100644 --- a/tests/c11.h +++ b/tests/c11.h @@ -6,12 +6,19 @@ #include #include +/** + * one way associative, single level + */ class C11 { public: - C11() : m_delay(4), c_delay(2), mem(new int), fetch(new int) + C11() { - this->c = new Cache(new Dram(this->m_delay), this->c_delay); + this->m_delay = 4; + this->c_delay = 2; + this->mem = new int(); + this->fetch = new int(); + this->c = new Cache(new Dram(this->m_delay), 5, this->c_delay); this->expected = {0, 0, 0, 0}; this->actual = this->c->view(0, 1)[0]; } diff --git a/tests/cache_2_1.cc b/tests/cache_2_1.cc new file mode 100644 index 0000000..101c6c3 --- /dev/null +++ b/tests/cache_2_1.cc @@ -0,0 +1,21 @@ +#include "c11.h" +#include "cache.h" +#include "dram.h" +#include "storage.h" +#include + +/** + * one way associative, two level + */ +class C21 : public C11 +{ + public: + C21() : C11() + { + Storage *s; + + s = new Dram(this->m_delay); + s = new Cache(s, 5, this->c_delay); + this->c = new Cache(s, 7, this->c_delay); + } +}; -- cgit v1.2.3 From 432e6f63ab4742ebf34ba7d031e269af810aa93f Mon Sep 17 00:00:00 2001 From: bd Date: Mon, 14 Apr 2025 20:19:32 -0400 Subject: Add two-level cache test --- inc/definitions.h | 2 +- tests/cache_1_1.cc | 6 ++--- tests/cache_2_1.cc | 78 +++++++++++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 76 insertions(+), 10 deletions(-) (limited to 'tests') diff --git a/inc/definitions.h b/inc/definitions.h index db43426..8513361 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -20,7 +20,7 @@ * The number of bits to specify a memory line * The total number of lines in memory */ -#define MEM_WORD_SPEC 10 +#define MEM_WORD_SPEC 16 #define MEM_LINE_SPEC static_cast(MEM_WORD_SPEC - LINE_SPEC) #define MEM_WORDS static_cast(pow(2, MEM_WORD_SPEC)) #define MEM_LINES static_cast(pow(2, MEM_LINE_SPEC)) diff --git a/tests/cache_1_1.cc b/tests/cache_1_1.cc index e3677a4..7d16f76 100644 --- a/tests/cache_1_1.cc +++ b/tests/cache_1_1.cc @@ -11,7 +11,7 @@ TEST_CASE_METHOD(C11, "store 0th element in DELAY cycles", "[dram]") w = 0x11223344; // delay + 1 due to internal logic, when mem - // finishes handle_miss still returns 'blocked' + // finishes is_address_missing still returns '1' this->wait_then_do(this->m_delay + this->c_delay + 1, [this, w]() { return this->c->write_word(this->mem, w, 0b0); }); @@ -32,7 +32,7 @@ TEST_CASE_METHOD(C11, "store 0th, 1st element in DELAY cycles, with conflict", " w = 0x11223344; // delay + 1 due to internal logic, when mem - // finishes handle_miss still returns 'blocked' + // finishes is_address_missing still returns '1' for (i = 0; i < this->m_delay + this->c_delay + 1; ++i) { r = c->write_word(this->mem, w, 0b0); CHECK(!r); @@ -72,7 +72,7 @@ TEST_CASE_METHOD( w = 0x11223344; // delay + 1 due to internal logic, when mem - // finishes handle_miss still returns 'blocked' + // finishes is_address_missing still returns '1' this->wait_then_do(this->m_delay + this->c_delay + 1, [this, w]() { return this->c->write_word(this->mem, w, 0b0); }); diff --git a/tests/cache_2_1.cc b/tests/cache_2_1.cc index 101c6c3..5b5a072 100644 --- a/tests/cache_2_1.cc +++ b/tests/cache_2_1.cc @@ -3,19 +3,85 @@ #include "dram.h" #include "storage.h" #include +#include /** - * one way associative, two level + * One way associative, two level + * Assuming that each address is 14 bits (16384 word address space): + * LEVEL1: OFFSET=2, INDEX=5(32), TAG=7 + * LEVEL2: OFFSET=2, INDEX=7(128), TAG=5 */ class C21 : public C11 { public: C21() : C11() { - Storage *s; - - s = new Dram(this->m_delay); - s = new Cache(s, 5, this->c_delay); - this->c = new Cache(s, 7, this->c_delay); + this->c2 = new Cache(new Dram(this->m_delay), 7, this->c_delay); + this->c = new Cache(this->c2, 5, this->c_delay); } + + Cache *c2; }; + +// TEST_CASE_METHOD(C21, "store 32th, 33rd element in DELAY cycles", + +TEST_CASE_METHOD(C21, "store 32th, 96th element in DELAY cycles, evict to level 2", "[2level_cache]") +{ + int r; + signed int w; + CHECK(expected == actual); + + w = 0x11223344; + // delay + 1 due to internal logic, when mem + // finishes handle_miss still returns 'blocked' + this->wait_then_do(this->m_delay + (this->c_delay * 2) + 2, [this, w]() { + return this->c->write_word(this->mem, w, 0b10000000); + }); + + r = this->c->write_word(this->mem, w, 0b10000000); + CHECK(r); + + // check level 2 + // note this is write-back == no write + actual = this->c2->view(32, 1)[0]; + REQUIRE(expected == actual); + + // check level 1 + expected.at(0) = w; + actual = this->c->view(0, 1)[0]; + REQUIRE(expected == actual); + + // wait = evict + this->wait_then_do(this->c_delay + 1, [this, w]() { + return this->c->write_word(this->mem, w, 0b110000000); + }); + + // check level 2 + actual = this->c2->view(32, 1)[0]; + REQUIRE(expected == actual); + + // read in line + this->wait_then_do(this->m_delay + this->c_delay + 1, [this, w]() { + return this->c->write_word(this->mem, w, 0b110000000); + }); + + expected.at(0) = 0; + // perform write + this->wait_then_do(this->c_delay + 1, [this, w]() { + return this->c->write_word(this->mem, w, 0b110000000); + }); + + r = this->c->write_word(this->mem, w, 0b110000000); + CHECK(r); + + // check level 2 + actual = this->c2->view(96, 1)[0]; + REQUIRE(expected == actual); + expected.at(0) = w; + actual = this->c2->view(32, 1)[0]; + REQUIRE(expected == actual); + + // check level 1 + actual = this->c->view(0, 1)[0]; + REQUIRE(expected == actual); +} -- cgit v1.2.3 From 71f69927931e007d0bac13b9268b6a697b45c70a Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 16 Apr 2025 11:23:46 -0400 Subject: Update GET_FIELDS to account for number of ways, constructors --- inc/cache.h | 18 +++++++++++++----- src/cache.cc | 29 ++++++++++++++++++----------- src/dram.cc | 5 +---- tests/c11.h | 2 +- tests/cache_2_1.cc | 4 ++-- 5 files changed, 35 insertions(+), 23 deletions(-) (limited to 'tests') diff --git a/inc/cache.h b/inc/cache.h index 7409c02..6f06466 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -17,8 +17,8 @@ */ // clang-format off #define GET_FIELDS(a, t, i, o) \ - *(t) = GET_MID_BITS(a, this->size + LINE_SPEC, MEM_WORD_SPEC); \ - *(i) = GET_MID_BITS(a, LINE_SPEC, this->size + LINE_SPEC); \ + *(t) = GET_MID_BITS(a, this->size + LINE_SPEC - this->ways, MEM_WORD_SPEC); \ + *(i) = GET_MID_BITS(a, LINE_SPEC, this->size + LINE_SPEC - this->ways); \ *(o) = GET_LS_BITS(a, LINE_SPEC) // clang-format on @@ -32,10 +32,12 @@ nn * Constructor. * @param The next lowest level in storage. Methods from this object are * called in case of a cache miss. * @param The number of bits required to specify a line in this level of cache. + * @param The number of ways this line of cache uses, or the number of data addresses stored for + * certain address index. * @param The number of clock cycles each access takes. * @return A new cache object. */ - Cache(Storage *lower, unsigned int size, int delay); + Cache(Storage *lower, unsigned int size, unsigned int ways, int delay); ~Cache(); int write_word(void *, signed int, int) override; @@ -44,7 +46,8 @@ nn * Constructor. int read_word(void *, int, signed int &) override; private: - int process(void *id, int address, std::function request_handler) override; + int process( + void *id, int address, std::function request_handler) override; /** * Helper for process. * Fetches `address` from a lower level of storage if it is not already @@ -57,13 +60,18 @@ nn * Constructor. * The number of bits required to specify a line in this level of cache. */ unsigned int size; + /** + * The number of bits required to specify a way, or the number of data addresses stored for + * certain address index. + */ + unsigned int ways; /** * An array of metadata about elements in `data`. * If the first value of an element is negative, the corresponding * element in `data` is invalid. If the most second value of an element * is nonzero, the corresponding element in `data` is dirty. */ - std::vector> meta; + std::vector> meta; }; #endif /* CACHE_H_INCLUDED */ diff --git a/src/cache.cc b/src/cache.cc index 68047ed..08545fd 100644 --- a/src/cache.cc +++ b/src/cache.cc @@ -3,15 +3,18 @@ #include #include -Cache::Cache(Storage *lower, unsigned int size, int delay) : Storage(delay) +Cache::Cache(Storage *lower, unsigned int size, unsigned int ways, int delay) : Storage(delay) { int true_size; true_size = 1 << size; this->data->resize(true_size); - this->meta = std::vector>(true_size, {-1, -1}); - this->size = size; + this->meta = std::vector>(true_size, {-1, -1, -1}); this->lower = lower; + + this->size = size; + // store the number of bits which are moved into the tag field + this->ways = ways; } Cache::~Cache() @@ -58,13 +61,7 @@ Cache::read_word(void *id, int address, signed int &data) int Cache::process(void *id, int address, std::function request_handler) { - if (!preprocess(id)) - return 0; - - if (is_address_missing(address)) - return 0; - - if (!this->is_data_ready()) + if (!preprocess(id) || is_address_missing(address) || !this->is_data_ready()) return 0; int tag, index, offset; @@ -79,7 +76,7 @@ Cache::is_address_missing(int expected) { int r, q, tag, index, offset; std::array *actual; - std::array *meta; + std::array *meta; GET_FIELDS(expected, &tag, &index, &offset); r = 0; @@ -104,3 +101,13 @@ Cache::is_address_missing(int expected) return r; } + +// unsigned int +// Cache::get_true_index(unsigned int index) +// { +// } + +// unsigned int +// Cache::get_replacement_index(unsigned int index) +// { +// } diff --git a/src/dram.cc b/src/dram.cc index bbd18b7..53db16b 100644 --- a/src/dram.cc +++ b/src/dram.cc @@ -54,10 +54,7 @@ Dram::load(std::vector program) int Dram::process(void *id, int address, std::function request_handler) { - if (!preprocess(id)) - return 0; - - if (!this->is_data_ready()) + if (!preprocess(id) || !this->is_data_ready()) return 0; int line, word; diff --git a/tests/c11.h b/tests/c11.h index 6d63c77..e5599db 100644 --- a/tests/c11.h +++ b/tests/c11.h @@ -18,7 +18,7 @@ class C11 this->c_delay = 2; this->mem = new int(); this->fetch = new int(); - this->c = new Cache(new Dram(this->m_delay), 5, this->c_delay); + this->c = new Cache(new Dram(this->m_delay), 5, 0, this->c_delay); this->expected = {0, 0, 0, 0}; this->actual = this->c->view(0, 1)[0]; } diff --git a/tests/cache_2_1.cc b/tests/cache_2_1.cc index 5b5a072..cb48d2a 100644 --- a/tests/cache_2_1.cc +++ b/tests/cache_2_1.cc @@ -16,8 +16,8 @@ class C21 : public C11 public: C21() : C11() { - this->c2 = new Cache(new Dram(this->m_delay), 7, this->c_delay); - this->c = new Cache(this->c2, 5, this->c_delay); + this->c2 = new Cache(new Dram(this->m_delay), 7, 0, this->c_delay); + this->c = new Cache(this->c2, 5, 0, this->c_delay); } Cache *c2; -- cgit v1.2.3