RISC-VECTOR.git, branch masterA simulator for the custom RISC-V[ECTOR] ISA written in C++https://git.operationnull.com/RISC-VECTOR.git/atom?h=master2025-05-12T03:39:06+00:00Merge pull request #79 from bdunahu/bdunahu2025-05-12T03:39:06+00:00Siddarth Suresh155843085+SiddarthSuresh98@users.noreply.github.com2025-05-12T03:39:06+00:00urn:sha1:f02bea04284d33a2d014f636baa6a861b73f6c41
Replace LOADV, STOREV, with strided load (SRDL), strided store (SRDS), add vector rotate (ROTV)Add ROTV instruction2025-05-12T02:04:46+00:00bdbdunahu@operationnull.com2025-05-12T02:04:46+00:00urn:sha1:43588597069587f6846a7d64a1957435bec5429dFix bug where vector registers were not cleared when length was 02025-05-12T02:04:12+00:00bdbdunahu@operationnull.com2025-05-12T02:04:12+00:00urn:sha1:e98aadede1f2151e50a8fdb3dc69d306590718ebStride load, stride store2025-05-11T23:40:47+00:00bdbdunahu@operationnull.com2025-05-11T23:40:47+00:00urn:sha1:c9d4b54150b67e1701a920719ba2c7c03d897d27Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general2025-05-11T17:08:16+00:00bdbdunahu@operationnull.com2025-05-11T17:08:16+00:00urn:sha1:79a68cabb033530871a1dab259149480584b2586Remove I_VECT field types2025-05-11T16:31:58+00:00bdbdunahu@operationnull.com2025-05-11T16:31:58+00:00urn:sha1:5326509d842c038a2d4f7dcf11fcadf960e437ddReplaced STOREV with LOADV2025-05-11T16:21:34+00:00bdbdunahu@operationnull.com2025-05-11T16:20:33+00:00urn:sha1:26c24ab3c581967015490d1a11ee098bb5ba338aMerge pull request #78 from bdunahu/bdunahu2025-05-11T15:51:15+00:00Siddarth Suresh155843085+SiddarthSuresh98@users.noreply.github.com2025-05-11T15:51:15+00:00urn:sha1:a35eb451889f0efa99ff7fe1c0a3a76afd5e7ad5
cleanup/fix existing vector extensionFix bug where too many vector elements were written back2025-05-11T02:28:01+00:00bdbdunahu@operationnull.com2025-05-11T02:28:01+00:00urn:sha1:6f4e9e0b914c3e68691a5d884cbad0b5813fcf18Fix off-by-one in CEV equal2025-05-11T01:24:41+00:00bdbdunahu@operationnull.com2025-05-11T01:24:41+00:00urn:sha1:2269a338f9e5ad7a29bef5ff73bbb4d72489a92e