RISC-VECTOR.git/gui, branch master A simulator for the custom RISC-V[ECTOR] ISA written in C++ https://git.operationnull.com/RISC-VECTOR.git/atom?h=master 2025-05-12T02:04:46+00:00 Add ROTV instruction 2025-05-12T02:04:46+00:00 bd bdunahu@operationnull.com 2025-05-12T02:04:46+00:00 urn:sha1:43588597069587f6846a7d64a1957435bec5429d Stride load, stride store 2025-05-11T23:40:47+00:00 bd bdunahu@operationnull.com 2025-05-11T23:40:47+00:00 urn:sha1:c9d4b54150b67e1701a920719ba2c7c03d897d27 Replaced STOREV with LOADV 2025-05-11T16:21:34+00:00 bd bdunahu@operationnull.com 2025-05-11T16:20:33+00:00 urn:sha1:26c24ab3c581967015490d1a11ee098bb5ba338a Fix vector register display from accessing oobs, REM instr display 2025-04-29T15:22:06+00:00 bd bdunahu@operationnull.com 2025-04-29T15:22:06+00:00 urn:sha1:de05860b750f00e6f9c16144d8949add66f1a785 Fix bug with pipeline blockage, swap DRAM delay to 100 2025-04-28T22:24:49+00:00 bd bdunahu@operationnull.com 2025-04-28T22:24:49+00:00 urn:sha1:930ec733e988c4996918065b4656f0508c6e2df6 Fix register display issue 2025-04-28T19:09:41+00:00 Siddarth-Suresh 65844402+Siddarth-Suresh@users.noreply.github.com 2025-04-28T19:09:41+00:00 urn:sha1:2859419b3e92a1558f83862f6e57d6c7e36ffe74 version bump 2025-04-28T03:57:31+00:00 bd bdunahu@operationnull.com 2025-04-28T03:57:31+00:00 urn:sha1:a872da5612eb73b841bdd052354a2f7b1007d873 Make cache generation more reasonable 2025-04-28T03:50:49+00:00 bd bdunahu@operationnull.com 2025-04-28T03:50:49+00:00 urn:sha1:ccd9b29afac5d745bba814551246edb7f681c711 Fix UI display to not be ridged 2025-04-28T03:34:35+00:00 bd bdunahu@operationnull.com 2025-04-28T03:34:35+00:00 urn:sha1:336faf3fd701aaf962613abd1ff0a69cbdf021ce Basic register display 2025-04-27T21:34:16+00:00 bd bdunahu@operationnull.com 2025-04-27T21:34:16+00:00 urn:sha1:4f77c3161128ff965b26f9575853c5347c0d662d