RISC-VECTOR.git/src/cli, branch master A simulator for the custom RISC-V[ECTOR] ISA written in C++ https://git.operationnull.com/RISC-VECTOR.git/atom?h=master 2025-04-12T03:09:49+00:00 Move storage to a separate git repository. 2025-04-12T03:09:49+00:00 bd bdunahu@operationnull.com 2025-04-12T03:09:49+00:00 urn:sha1:df580c5352528a4837b996a838f486d3838050a4 get_instr_fields return mnemonic rather than opcode and type 2025-03-29T06:36:38+00:00 bd bdunahu@operationnull.com 2025-03-29T06:36:38+00:00 urn:sha1:bc47d9131869b1f072e21d9cb61746d14bf30751 Remove manual clock advancing / resolution from storage devices 2025-03-22T18:38:35+00:00 bd bdunahu@operationnull.com 2025-03-22T18:38:35+00:00 urn:sha1:f2973132685fe908a2dd651ea0b347456c911f37 Rewrite all Dram tests to use Fixture 2025-03-20T23:28:57+00:00 bd bdunahu@operationnull.com 2025-03-20T23:28:57+00:00 urn:sha1:cf3ac49639bef5082489068e2d92a4d86f42080b Call memory wrapping functions properly 2025-03-11T21:33:27+00:00 bd bdunahu@operationnull.com 2025-03-11T21:33:27+00:00 urn:sha1:1e095065907c2ab7b3a9705fab7c44e60361e035 clarify macro names, implement load in CLI, fix many display issues 2025-03-11T21:24:49+00:00 bd bdunahu@operationnull.com 2025-03-11T21:24:49+00:00 urn:sha1:979723533989a38660ece630b9e458cb3aa61bda Merge remote-tracking branch 'origin/master' into bdunahu 2025-03-11T21:24:37+00:00 bd bdunahu@operationnull.com 2025-03-11T21:24:37+00:00 urn:sha1:282aff5a3d1b6f9678453dfa3e216849d5b1d954 Rename read/write to read_line and write_word 2025-03-11T20:39:47+00:00 bd bdunahu@operationnull.com 2025-03-11T20:39:47+00:00 urn:sha1:d534555fbb9562a819d34ea874a711d737d051ae Clarify size of mem and cache in definitions, CLI print invalid tags 2025-03-11T15:54:21+00:00 bd bdunahu@operationnull.com 2025-03-11T15:54:21+00:00 urn:sha1:a59c031ca0521bfb00bfc5f8f65af45c89804a37 fix namespace issues with match function 2025-03-11T14:50:11+00:00 bd bdunahu@operationnull.com 2025-03-11T14:50:11+00:00 urn:sha1:ceff6a4d11b93130b9b1f13c1ce8e51490ffd188