RISC-VECTOR.git/src/storage, branch masterA simulator for the custom RISC-V[ECTOR] ISA written in C++https://git.operationnull.com/RISC-VECTOR.git/atom?h=master2025-04-12T03:09:49+00:00Move storage to a separate git repository.2025-04-12T03:09:49+00:00bdbdunahu@operationnull.com2025-04-12T03:09:49+00:00urn:sha1:df580c5352528a4837b996a838f486d3838050a4add get_instr_fields func to parse instruction fields from raw bits2025-03-28T22:10:14+00:00bdbdunahu@operationnull.com2025-03-28T22:10:14+00:00urn:sha1:9cd1f287f0c86b36788cd8ede812b847c584f711Add fetch stage implementation, tests, program loading, DTO object2025-03-26T16:21:52+00:00bdbdunahu@operationnull.com2025-03-26T16:21:52+00:00urn:sha1:b81c86b438123457be86af2e7c24375856afa742Merge pull request #30 from bdunahu/bdunahu2025-03-23T17:47:34+00:00bdbdunaisky@umass.edu2025-03-23T17:47:34+00:00urn:sha1:877aa98855fad77ef93a8c9f5a5e8191fbb9e699
Add controller.h, implementation and tests.Remove manual clock advancing / resolution from storage devices2025-03-22T18:38:35+00:00bdbdunahu@operationnull.com2025-03-22T18:38:35+00:00urn:sha1:f2973132685fe908a2dd651ea0b347456c911f37Add controller.h, implementation and tests.2025-03-22T18:19:10+00:00bdbdunahu@operationnull.com2025-03-22T18:19:10+00:00urn:sha1:2416cce2eec7ecdf0587896620806c465747eadaadd 'process' function to handle boilerplate on every request2025-03-21T20:42:16+00:00bdbdunahu@operationnull.com2025-03-21T20:42:16+00:00urn:sha1:a29cd5297d2d66f05ea91d05175fdc9fd4b2fef3Small cleanups to up a lot of inplementation details2025-03-21T20:06:07+00:00bdbdunahu@operationnull.com2025-03-21T20:06:07+00:00urn:sha1:431cba9a4bcef0e0ae047d45a7f3d98e601e30edRewrite current cache.cc tests, add test-helper function to dram2025-03-21T05:06:38+00:00bdbdunahu@operationnull.com2025-03-21T05:06:38+00:00urn:sha1:91886988ddfd276cd6e51f05b9e92fd1926b54ecRewrite all Dram tests to use Fixture2025-03-20T23:28:57+00:00bdbdunahu@operationnull.com2025-03-20T23:28:57+00:00urn:sha1:cf3ac49639bef5082489068e2d92a4d86f42080b