RISC-VECTOR.git/src/utils, branch master A simulator for the custom RISC-V[ECTOR] ISA written in C++ https://git.operationnull.com/RISC-VECTOR.git/atom?h=master 2025-04-23T00:55:05+00:00 Remove subfolders 2025-04-23T00:55:05+00:00 bd bdunahu@operationnull.com 2025-04-23T00:55:05+00:00 urn:sha1:baacedcc858d8d4857282cc7fb1881a11048a5bc Remove the accessor object 2025-04-23T00:49:26+00:00 bd bdunahu@operationnull.com 2025-04-23T00:49:26+00:00 urn:sha1:95d09e12792cf5ececd32b8dc84f2cd090c496ef Add licensing information 2025-04-21T15:14:32+00:00 bd bdunahu@operationnull.com 2025-04-21T15:14:32+00:00 urn:sha1:4a19129e8499bc187ef6e296e050cc8a20bcc2d3 Delete some more storage-only files 2025-04-12T04:10:52+00:00 bd bdunahu@operationnull.com 2025-04-12T04:10:52+00:00 urn:sha1:249e5bc94ef86307ecf68f8a07c65b2672ebb21c Add implementation functions for checking out a register. 2025-03-29T16:30:54+00:00 bd bdunahu@operationnull.com 2025-03-29T16:30:54+00:00 urn:sha1:9793bf119cc6314e264bdfc9e98bc27c81db0adb Move get_instr_fields, add all instruction mnemonics 2025-03-28T23:55:04+00:00 bd bdunahu@operationnull.com 2025-03-28T23:55:04+00:00 urn:sha1:7b3abbd51c91b51725a12d17fad6ecbfcdb19975 add get_instr_fields func to parse instruction fields from raw bits 2025-03-28T22:10:14+00:00 bd bdunahu@operationnull.com 2025-03-28T22:10:14+00:00 urn:sha1:9cd1f287f0c86b36788cd8ede812b847c584f711 Instr, InstrDTO gets/sets, other structures required for decode 2025-03-28T00:30:18+00:00 bd bdunahu@operationnull.com 2025-03-28T00:30:18+00:00 urn:sha1:eaa87e9fcd90c00d6261cbdb854efb7a09467f1d Small cleanups to up a lot of inplementation details 2025-03-21T20:06:07+00:00 bd bdunahu@operationnull.com 2025-03-21T20:06:07+00:00 urn:sha1:431cba9a4bcef0e0ae047d45a7f3d98e601e30ed fix lots of bugs 2025-03-11T23:02:55+00:00 bd bdunahu@operationnull.com 2025-03-11T23:02:55+00:00 urn:sha1:f3d6ceaa6f0d716a4b0d30c5c8b27c74c55b96ac