RISC-VECTOR.git/src, branch master A simulator for the custom RISC-V[ECTOR] ISA written in C++ https://git.operationnull.com/RISC-VECTOR.git/atom?h=master 2025-05-12T02:04:46+00:00 Add ROTV instruction 2025-05-12T02:04:46+00:00 bd bdunahu@operationnull.com 2025-05-12T02:04:46+00:00 urn:sha1:43588597069587f6846a7d64a1957435bec5429d Fix bug where vector registers were not cleared when length was 0 2025-05-12T02:04:12+00:00 bd bdunahu@operationnull.com 2025-05-12T02:04:12+00:00 urn:sha1:e98aadede1f2151e50a8fdb3dc69d306590718eb Stride load, stride store 2025-05-11T23:40:47+00:00 bd bdunahu@operationnull.com 2025-05-11T23:40:47+00:00 urn:sha1:c9d4b54150b67e1701a920719ba2c7c03d897d27 Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general 2025-05-11T17:08:16+00:00 bd bdunahu@operationnull.com 2025-05-11T17:08:16+00:00 urn:sha1:79a68cabb033530871a1dab259149480584b2586 Remove I_VECT field types 2025-05-11T16:31:58+00:00 bd bdunahu@operationnull.com 2025-05-11T16:31:58+00:00 urn:sha1:5326509d842c038a2d4f7dcf11fcadf960e437dd Replaced STOREV with LOADV 2025-05-11T16:21:34+00:00 bd bdunahu@operationnull.com 2025-05-11T16:20:33+00:00 urn:sha1:26c24ab3c581967015490d1a11ee098bb5ba338a Fix bug where too many vector elements were written back 2025-05-11T02:28:01+00:00 bd bdunahu@operationnull.com 2025-05-11T02:28:01+00:00 urn:sha1:6f4e9e0b914c3e68691a5d884cbad0b5813fcf18 Fix off-by-one in CEV equal 2025-05-11T01:24:41+00:00 bd bdunahu@operationnull.com 2025-05-11T01:24:41+00:00 urn:sha1:2269a338f9e5ad7a29bef5ff73bbb4d72489a92e Fix overflow/underflow conditions in vector ops 2025-05-11T01:15:24+00:00 bd bdunahu@operationnull.com 2025-05-11T01:15:24+00:00 urn:sha1:714622080d510de1591de2c689d8bd319b54f432 Separate ex advance into methods handling different field types 2025-05-11T00:35:18+00:00 bd bdunahu@operationnull.com 2025-05-11T00:35:18+00:00 urn:sha1:727afe4ffac0f193696c99234a2ade3a02f73157