RISC-VECTOR.git/tests, branch master A simulator for the custom RISC-V[ECTOR] ISA written in C++ https://git.operationnull.com/RISC-VECTOR.git/atom?h=master 2025-05-11T16:21:34+00:00 Replaced STOREV with LOADV 2025-05-11T16:21:34+00:00 bd bdunahu@operationnull.com 2025-05-11T16:20:33+00:00 urn:sha1:26c24ab3c581967015490d1a11ee098bb5ba338a Fix issue where decode would overwrite raw bits while in use 2025-05-10T21:02:27+00:00 bd bdunahu@operationnull.com 2025-05-10T21:02:27+00:00 urn:sha1:f0f773a1f2acc3030c89fc5aa6335f667987aa2a Combine read_vec_guard and read_guard using templates 2025-05-10T19:17:40+00:00 bd bdunahu@operationnull.com 2025-05-10T19:17:40+00:00 urn:sha1:d0bb0aaf39bb61736e72b30e4d8f1a4a39536a0c Fix tests to use correct register indexes with vector addition 2025-05-10T19:07:58+00:00 bd bdunahu@operationnull.com 2025-05-10T19:07:58+00:00 urn:sha1:a08582325ef39cb5dc1bbe14043b756b111899b1 Rename Response.WAIT to READY, delete BLOCKED 2025-04-23T04:47:24+00:00 bd bdunahu@operationnull.com 2025-04-23T04:47:24+00:00 urn:sha1:8e33ba4499bced747f66ed436211876d220342d6 Move dum class to tests folder 2025-04-23T04:27:50+00:00 bd bdunahu@operationnull.com 2025-04-23T04:27:50+00:00 urn:sha1:051041c9cbe0752a50ac1a464df1c554b10cde0c Use a struct for InstrDTO 2025-04-23T03:39:14+00:00 bd bdunahu@operationnull.com 2025-04-23T03:39:14+00:00 urn:sha1:302bbdc7ac18cd355f9f081cae202f5434427262 Properly set condition codes for all operations sub SHIFTs 2025-04-22T06:16:10+00:00 bd bdunahu@operationnull.com 2025-04-22T06:16:10+00:00 urn:sha1:86a6253a2fb2d016a63e57d6a5e5461df87668e5 Add option to turn off pipeline 2025-04-17T23:56:53+00:00 bd bdunahu@operationnull.com 2025-04-17T23:56:53+00:00 urn:sha1:984ce6eef2e439955ff991f90c2b654be7c6c3f3 Fix the tests which could be fixed, delete others 2025-04-17T21:51:17+00:00 bd bdunahu@operationnull.com 2025-04-17T21:51:17+00:00 urn:sha1:082200691a5d95f716a9d1dc127c858322cdff37