diff options
Diffstat (limited to 'inc')
| -rw-r--r-- | inc/ex.h | 2 | ||||
| -rw-r--r-- | inc/id.h | 2 | ||||
| -rw-r--r-- | inc/if.h | 12 | ||||
| -rw-r--r-- | inc/mm.h | 2 | ||||
| -rw-r--r-- | inc/stage.h | 26 | ||||
| -rw-r--r-- | inc/wb.h | 2 |
6 files changed, 32 insertions, 14 deletions
@@ -14,7 +14,7 @@ class EX : public Stage */ EX(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; }; #endif /* EX_H_INCLUDED */ @@ -15,7 +15,7 @@ class ID : public Stage */ ID(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; /** * Parse an instruction into a type, opcode, and fields. If the type is @@ -15,7 +15,17 @@ class IF : public Stage */ IF(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; + + private: + /** + * Performs a fetch only if a current fetch is not pending. Pending means + * that a fetch has completed successfully, but the caller stage in the + * pipeline is not ready to receive it. In this case, `curr_instr` is not + * the nullptr. + * @return STALLED if we are waiting on the storage devices, OK otherwise. + */ + void fetch_with_buffer(); }; #endif /* IF_H_INCLUDED */ @@ -14,7 +14,7 @@ class MM : public Stage */ MM(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; }; #endif /* MM_H_INCLUDED */ diff --git a/inc/stage.h b/inc/stage.h index 761b9f6..ff4455b 100644 --- a/inc/stage.h +++ b/inc/stage.h @@ -7,6 +7,7 @@ #include "storage.h" #include <array> #include <set> +#include <memory> class Stage { @@ -17,17 +18,16 @@ class Stage * @return A newly allocated stage object. */ Stage(Stage *next); - virtual ~Stage() = default; + virtual ~Stage(); /** * Advances this stage by a single clock cycle. - * @param a DTO object containing various information about an instruction - * moving through the pipeline. + * @param a DTO object containing the next instruction to be processed. * @param a response, indicating whether or not the parent pipe stage is - * busy. + * ready to accept a new instruction object next cycle. * @return a response, indicating whether this pipeline stage is stalling, * busy, or done. */ - virtual Response advance(InstrDTO &i, Response p) = 0; + virtual Response advance(InstrDTO &next_instr, Response p) = 0; protected: /** @@ -57,10 +57,6 @@ class Stage */ static unsigned int pc; /** - * A pointer to the next stage in the pipeline. - */ - Stage *next; - /** * A pointer to the top-level storage device. */ static Storage *storage; @@ -72,6 +68,18 @@ class Stage * The current clock cycle. */ static int clock_cycle; + /** + * A pointer to the next stage in the pipeline. + */ + Stage *next; + /** + * A pointer to the current instruction this stage is processing. + */ + std::unique_ptr<InstrDTO> curr_instr; + /** + * The current status of this stage. + */ + Response status; private: /** @@ -14,7 +14,7 @@ class WB : public Stage */ WB(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; }; #endif /* WB_H_INCLUDED */ |