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-rw-r--r--src/sim/dum.cc2
-rw-r--r--src/sim/ex.cc17
-rw-r--r--src/sim/id.cc72
-rw-r--r--src/sim/if.cc5
-rw-r--r--src/sim/instr.cc13
-rw-r--r--src/sim/instrDTO.cc12
-rw-r--r--src/sim/stage.cc27
-rw-r--r--src/sim/wb.cc16
8 files changed, 88 insertions, 76 deletions
diff --git a/src/sim/dum.cc b/src/sim/dum.cc
index 76d4acd..ab4eaa4 100644
--- a/src/sim/dum.cc
+++ b/src/sim/dum.cc
@@ -3,7 +3,6 @@
#include "instrDTO.h"
#include "response.h"
#include "stage.h"
-#include "utils.h"
DUM::DUM(Stage *stage) : Stage(stage) { this->id = IDLE; }
@@ -12,7 +11,6 @@ InstrDTO *DUM::advance(Response p)
InstrDTO *r = nullptr;
if (this->curr_instr && p == WAIT) {
- this->curr_instr->set_time_of(this->id, this->clock_cycle);
r = new InstrDTO(*this->curr_instr);
delete this->curr_instr;
curr_instr = nullptr;
diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index 50f00a8..d20d15f 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -1,10 +1,9 @@
#include "ex.h"
#include "accessor.h"
-#include "pipe_spec.h"
#include "instrDTO.h"
+#include "pipe_spec.h"
#include "response.h"
#include "stage.h"
-#include "utils.h"
#include <unordered_map>
// clang-format off
@@ -313,32 +312,28 @@ EX::EX(Stage *stage) : Stage(stage)
INIT_INSTRUCTION(
BEQ,
{
- (this->get_condition(EQ)) ? s1 = wrap_address(pc + s2)
- : s1 = -1;
+ (this->get_condition(EQ)) ? s1 = pc + s2 : s1 = -1;
(void)s3;
}),
INIT_INSTRUCTION(
BGT,
{
- (this->get_condition(GT)) ? s1 = wrap_address(pc + s2)
- : s1 = -1;
+ (this->get_condition(GT)) ? s1 = pc + s2 : s1 = -1;
(void)s3;
}),
INIT_INSTRUCTION(
BUF,
{
- (this->get_condition(UF)) ? s1 = wrap_address(pc + s2)
- : s1 = -1;
+ (this->get_condition(UF)) ? s1 = pc + s2 : s1 = -1;
(void)s3;
}),
INIT_INSTRUCTION(
BOF,
{
- (this->get_condition(OF)) ? s1 = wrap_address(pc + s2)
- : s1 = -1;
+ (this->get_condition(OF)) ? s1 = pc + s2 : s1 = -1;
(void)s3;
}),
@@ -387,7 +382,7 @@ void EX::advance_helper()
s3 = this->curr_instr->get_s3();
pc = this->curr_instr->get_pc();
- this->instr_map[m](s1, s2, s3, pc );
+ this->instr_map[m](s1, s2, s3, pc);
this->curr_instr->set_s1(s1);
this->status = OK;
diff --git a/src/sim/id.cc b/src/sim/id.cc
index 46694ad..37c6773 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -38,7 +38,13 @@ Response ID::read_guard(signed int &v)
void ID::write_guard(signed int &v)
{
- this->checked_out.push_back(v);
+ // zero register shouldn't be written.
+ if (v != 0) {
+ // keep track in the instrDTO for displaying to user and writeback
+ // keep track in checked_out so we can still access this information!
+ this->checked_out.push_back(v);
+ this->curr_instr->set_checked_out(v);
+ }
v = this->dereference_register(v);
}
@@ -72,7 +78,7 @@ void ID::get_instr_fields(
switch (type) {
case 0b00:
t = R;
- this->decode_R_type(s1, s2, s3);
+ this->decode_R_type(s1, s2, s3, m);
break;
case 0b01:
t = I;
@@ -88,7 +94,8 @@ void ID::get_instr_fields(
}
}
-void ID::decode_R_type(signed int &s1, signed int &s2, signed int &s3)
+void ID::decode_R_type(
+ signed int &s1, signed int &s2, signed int &s3, Mnemonic &m)
{
unsigned int s0b, s1b, s2b;
Response r1, r2;
@@ -104,30 +111,52 @@ void ID::decode_R_type(signed int &s1, signed int &s2, signed int &s3)
r2 = this->read_guard(s2);
this->status = (r1 == OK && r2 == OK) ? OK : STALLED;
- if (this->status == OK)
- this->write_guard(s3);
+ switch (m) {
+ case CMP:
+ case CEV:
+ break;
+ default:
+ if (this->status == OK)
+ this->write_guard(s3);
+ }
}
void ID::decode_I_type(
signed int &s1, signed int &s2, signed int &s3, Mnemonic &m)
{
unsigned int s0b, s1b, s2b;
- Response r1;
+ Response r1, r2;
s0b = REG_SIZE;
s1b = s0b + REG_SIZE;
- s2b = WORD_SPEC;
- s3 = GET_MID_BITS(s1, s1b, s2b);
- s2 = GET_MID_BITS(s1, s0b, s1b);
- s1 = GET_LS_BITS(s1, s0b);
+ s2b = WORD_SPEC - LINE_SPEC - OPCODE_SIZE;
+ s3 = GET_BITS_SIGN_EXTEND(s1, s1b, s2b);
+
+ switch (m) {
+ case STORE:
+ case STOREV:
+ s2 = GET_MID_BITS(s1, s0b, s1b);
+ s1 = GET_LS_BITS(s1, s0b);
+
+ // both operands are read values
+ r1 = this->read_guard(s1);
+ r2 = this->read_guard(s2);
+ this->status = (r1 == OK && r2 == OK) ? OK : STALLED;
+ return;
+ case LOAD:
+ case LOADV:
+ s2 = GET_LS_BITS(s1, s0b);
+ s1 = GET_MID_BITS(s1, s0b, s1b);
+ break;
+ default:
+ s2 = GET_MID_BITS(s1, s0b, s1b);
+ s1 = GET_LS_BITS(s1, s0b);
+ }
r1 = this->read_guard(s1);
- if (m != STORE && m != STOREV) {
- this->status = r1;
- if (r1 == OK)
- this->write_guard(s2);
- } else
- this->status = (this->read_guard(s2) == OK && r1 == OK) ? OK : STALLED;
+ if (r1 == OK)
+ this->write_guard(s2);
+ this->status = r1;
}
void ID::decode_J_type(signed int &s1, signed int &s2, signed int &s3)
@@ -135,19 +164,20 @@ void ID::decode_J_type(signed int &s1, signed int &s2, signed int &s3)
unsigned int s0b, s1b;
s0b = REG_SIZE;
- s1b = WORD_SPEC;
+ s1b = WORD_SPEC - LINE_SPEC - OPCODE_SIZE;
s3 = 0;
- s2 = GET_MID_BITS(s1, s0b, s1b);
+ s2 = GET_BITS_SIGN_EXTEND(s1, s0b, s1b);
s1 = GET_LS_BITS(s1, s0b);
this->status = this->read_guard(*&s1);
}
-std::vector<int> ID::stage_info() {
+std::vector<int> ID::stage_info()
+{
std::vector<int> info;
- if(this->curr_instr){
+ if (this->curr_instr) {
info.push_back(this->curr_instr->get_pc());
info.push_back(this->curr_instr->get_instr_bits());
- }
+ }
return info;
}
diff --git a/src/sim/if.cc b/src/sim/if.cc
index fb49749..1223149 100644
--- a/src/sim/if.cc
+++ b/src/sim/if.cc
@@ -14,7 +14,6 @@ InstrDTO *IF::advance(Response p)
if (this->curr_instr != nullptr && p == WAIT) {
// mutual consent
++this->pc;
- this->curr_instr->set_time_of(this->id, this->clock_cycle);
r = new InstrDTO(*this->curr_instr);
delete curr_instr;
curr_instr = nullptr;
@@ -23,12 +22,12 @@ InstrDTO *IF::advance(Response p)
return r;
}
-std::vector<int> IF::stage_info() {
+std::vector<int> IF::stage_info() {
std::vector<int> info;
if(this->curr_instr){
info.push_back(this->curr_instr->get_pc());
info.push_back(this->curr_instr->get_instr_bits());
- }
+ }
return info;
}
diff --git a/src/sim/instr.cc b/src/sim/instr.cc
index e614de5..8bbd0b5 100644
--- a/src/sim/instr.cc
+++ b/src/sim/instr.cc
@@ -13,12 +13,11 @@ const std::unordered_map<unsigned int, Mnemonic> mnemonic_map = {
{0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV},
{0b1000000, CMP}, {0b1000100, CEV}, {0b000101, LOAD},
{0b001001, LOADV}, {0b0001101, ADDI}, {0b0010001, SUBI},
- {0b0010101, SFTRI}, {0b0011101, SFTLI}, {0b0100001, ANDI},
- {0b0100101, ORI}, {0b0101001, XORI}, {0b0101101, STORE},
- {0b0110001, STOREV}, {0b0000101, CEV}, {0b0000101, LOAD},
- {0b0001001, LOADV}, {0b0001001, LOADV}, {0b0000110, JMP},
- {0b0001010, JRL}, {0b0001110, JAL}, {0b0010010, BEQ},
- {0b0010110, BGT}, {0b0011010, BUF}, {0b0011110, BOF},
- {0b0100010, PUSH}, {0b0100110, POP},
+ {0b0010101, SFTRI}, {0b0011001, SFTLI}, {0b0011101, ANDI},
+ {0b0100001, ORI}, {0b0100101, XORI}, {0b0101001, STORE},
+ {0b0101101, STOREV}, {0b0000110, JMP}, {0b0001010, JRL},
+ {0b0001110, JAL}, {0b0010010, BEQ}, {0b0010110, BGT},
+ {0b0011010, BUF}, {0b0011110, BOF}, {0b0100010, PUSH},
+ {0b0100110, POP},
};
} // namespace instr
diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc
index aa49b7e..a82ef28 100644
--- a/src/sim/instrDTO.cc
+++ b/src/sim/instrDTO.cc
@@ -4,6 +4,7 @@
InstrDTO::InstrDTO()
{
this->instr_bits = 0;
+ this->checked_out = -1;
this->s1 = 0;
this->s2 = 0;
this->s3 = 0;
@@ -12,10 +13,10 @@ InstrDTO::InstrDTO()
this->pc = 0;
}
-int InstrDTO::get_time_of(Accessor a) { return this->hist[a]; }
-
signed int InstrDTO::get_instr_bits() { return this->instr_bits; }
+signed int InstrDTO::get_checked_out() { return this->checked_out; }
+
signed int InstrDTO::get_s1() { return this->s1; }
signed int InstrDTO::get_s2() { return this->s2; }
@@ -28,10 +29,13 @@ Type InstrDTO::get_type() { return this->type; }
unsigned int InstrDTO::get_pc() { return this->pc; }
-void InstrDTO::set_time_of(Accessor a, int i) { this->hist[a] = i; }
-
void InstrDTO::set_instr_bits(signed int instr) { this->instr_bits = instr; }
+void InstrDTO::set_checked_out(signed int checked_out)
+{
+ this->checked_out = checked_out;
+}
+
void InstrDTO::set_s1(signed int s) { this->s1 = s; }
void InstrDTO::set_s2(signed int s) { this->s2 = s; }
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 8a570f0..7df1dba 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -1,5 +1,4 @@
#include "stage.h"
-#include "utils.h"
#include <array>
#include <deque>
@@ -28,18 +27,17 @@ InstrDTO *Stage::advance(Response p)
InstrDTO *s = nullptr;
Response n;
- // std::cout << "advance: " << this->id << ": " << this->curr_instr << "?: " << p << ": " << this->checked_out.size() << ": ";
- // if (curr_instr)
+ // std::cout << "advance: " << this->id << ": " << this->curr_instr << "?: "
+ // << p << ": " << this->checked_out.size() << ": "; if (curr_instr)
// std::cout << curr_instr->get_mnemonic();
// for (long unsigned int i = 0; i < this->checked_out.size(); ++i)
// std::cout << this->checked_out[i] << " ";
- // std::cout << std::endl;
+ // std::cout << std::endl;
if (this->curr_instr && this->status != OK) {
this->advance_helper();
}
if (this->status == OK && p == WAIT && this->curr_instr) {
// mutual consent
- this->curr_instr->set_time_of(this->id, this->clock_cycle);
r = new InstrDTO(*this->curr_instr);
delete curr_instr;
curr_instr = nullptr;
@@ -53,9 +51,10 @@ InstrDTO *Stage::advance(Response p)
return r;
}
-std::vector<int> Stage::stage_info() {
+std::vector<int> Stage::stage_info()
+{
std::vector<int> info;
- if(this->curr_instr){
+ if (this->curr_instr) {
info.push_back(this->curr_instr->get_mnemonic());
info.push_back(this->curr_instr->get_pc());
info.push_back(this->curr_instr->get_s1());
@@ -63,7 +62,7 @@ std::vector<int> Stage::stage_info() {
info.push_back(this->curr_instr->get_s3());
}
return info;
- }
+}
void Stage::set_condition(CC c, bool v)
{
@@ -78,10 +77,8 @@ signed int Stage::dereference_register(signed int v)
signed int r;
if (v < 0 || v >= GPR_NUM + V_NUM) {
- throw std::out_of_range(string_format(
- "instruction tried to access register %d, which does "
- "not exist",
- v));
+ throw std::out_of_range(
+ "instruction tried to access register which does not exist");
}
r = (v >= GPR_NUM) ? this->vrs[v % GPR_NUM] : this->gprs[v];
@@ -91,10 +88,8 @@ signed int Stage::dereference_register(signed int v)
void Stage::store_register(signed int v, signed int d)
{
if (v < 0 || v >= GPR_NUM + V_NUM) {
- throw std::out_of_range(string_format(
- "instruction tried to access register %d, which does "
- "not exist",
- v));
+ throw std::out_of_range(
+ "instruction tried to access register which does not exist");
}
if (v >= GPR_NUM)
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 01768e8..4e6b2b0 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -3,6 +3,8 @@
#include "instrDTO.h"
#include "response.h"
#include "stage.h"
+#include <array>
+#include <algorithm>
WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }
@@ -10,7 +12,7 @@ void WB::advance_helper()
{
if (this->curr_instr->get_mnemonic() != NOP &&
this->curr_instr->get_type() != INV) {
- if (this->should_write())
+ if (this->curr_instr->get_checked_out() > 0)
this->write_handler();
else if (this->should_jump())
this->jump_handler();
@@ -26,8 +28,8 @@ void WB::write_handler()
throw std::runtime_error("instruction tried to pop a register out of "
"an empty queue during writeback.");
- reg = this->checked_out.front();
this->checked_out.pop_front();
+ reg = this->curr_instr->get_checked_out();
this->store_register(reg, this->curr_instr->get_s1());
}
@@ -49,13 +51,3 @@ bool WB::should_jump()
t = this->curr_instr->get_type();
return t == J;
}
-
-bool WB::should_write()
-{
- Mnemonic m;
- Type t;
-
- m = this->curr_instr->get_mnemonic();
- t = this->curr_instr->get_type();
- return (t == R || t == I) && (m != STORE && m != STOREV);
-}
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-13 13:51:41 +0000