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-rw-r--r--src/sim/controller.cc4
-rw-r--r--src/sim/ex.cc2
-rw-r--r--src/sim/id.cc11
-rw-r--r--src/sim/if.cc30
-rw-r--r--src/sim/instrDTO.cc1
-rw-r--r--src/sim/mm.cc2
-rw-r--r--src/sim/stage.cc11
-rw-r--r--src/sim/wb.cc2
8 files changed, 43 insertions, 20 deletions
diff --git a/src/sim/controller.cc b/src/sim/controller.cc
index 833d900..17937eb 100644
--- a/src/sim/controller.cc
+++ b/src/sim/controller.cc
@@ -29,11 +29,11 @@ std::array<int, GPR_NUM> Controller::get_gprs() { return this->gprs; }
int Controller::get_pc() { return this->pc; }
-Response Controller::advance(InstrDTO &i, Response p)
+Response Controller::advance(InstrDTO &next_instr, Response p)
{
Response r;
- r = this->next->advance(i, p);
+ r = this->next->advance(next_instr, p);
++this->clock_cycle;
return r;
}
diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index c9c2116..5b561f8 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -6,4 +6,4 @@
EX::EX(Stage *stage) : Stage(stage) { this->id = EXEC; }
-Response EX::advance(InstrDTO &i, Response p) { return OK; }
+Response EX::advance(InstrDTO &next_instr, Response p) { return OK; }
diff --git a/src/sim/id.cc b/src/sim/id.cc
index 70fab9a..83a8751 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -8,15 +8,16 @@
ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; }
-Response ID::advance(InstrDTO &i, Response p)
+Response ID::advance(InstrDTO &next_instr, Response p)
{
Response r;
- signed int s1, s2, s3;
- Mnemonic m;
+ r = OK;
+ // signed int s1, s2, s3;
+ // Mnemonic m;
- s1 = i.get_instr_bits();
+ // s1 = next_instr.get_instr_bits();
- get_instr_fields(s1, s2, s3, m);
+ // get_instr_fields(s1, s2, s3, m);
return r;
}
diff --git a/src/sim/if.cc b/src/sim/if.cc
index 099ff1c..de044f8 100644
--- a/src/sim/if.cc
+++ b/src/sim/if.cc
@@ -6,17 +6,31 @@
IF::IF(Stage *stage) : Stage(stage) { this->id = FETCH; }
-Response IF::advance(InstrDTO &i, Response p)
+Response IF::advance(InstrDTO &next_instr, Response p)
+{
+ this->fetch_with_buffer();
+ if (this->status == OK && p == OK) {
+ // mutual consent
+ ++this->pc;
+ this->curr_instr->set_time_of(this->id, this->clock_cycle);
+ next_instr = *this->curr_instr;
+ curr_instr = nullptr;
+ }
+ return this->status;
+}
+
+void IF::fetch_with_buffer()
{
Response r;
signed int bits;
- r = this->storage->read_word(this->id, this->pc, bits);
- if (r == OK) {
- ++this->pc;
- i.set_time_of(this->id, this->clock_cycle);
- i.set_instr_bits(bits);
+ if (this->curr_instr == nullptr) {
+ r = this->storage->read_word(this->id, this->pc, bits);
+ if (r == OK) {
+ this->status = r;
+ this->curr_instr = std::make_unique<InstrDTO>();
+ this->curr_instr->set_instr_bits(bits);
+ } else
+ this->status = STALLED;
}
-
- return r;
}
diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc
index 7418033..5a7fe3b 100644
--- a/src/sim/instrDTO.cc
+++ b/src/sim/instrDTO.cc
@@ -7,6 +7,7 @@ InstrDTO::InstrDTO()
this->s1 = 0;
this->s2 = 0;
this->s3 = 0;
+ this->mnemonic = NOP;
}
int InstrDTO::get_time_of(Accessor a) { return this->hist[a]; }
diff --git a/src/sim/mm.cc b/src/sim/mm.cc
index 93c5b87..f394420 100644
--- a/src/sim/mm.cc
+++ b/src/sim/mm.cc
@@ -6,7 +6,7 @@
MM::MM(Stage *stage) : Stage(stage) { this->id = MEM; }
-Response MM::advance(InstrDTO &i, Response p)
+Response MM::advance(InstrDTO &next_instr, Response p)
{
return OK;
}
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 8d9dfc0..48ee494 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -5,7 +5,14 @@
static Logger *global_log = Logger::getInstance();
-Stage::Stage(Stage *next) { this->next = next; }
+Stage::Stage(Stage *next)
+{
+ this->next = next;
+ this->curr_instr = nullptr;
+ this->status = OK;
+}
+
+Stage::~Stage() { delete this->next; };
std::array<int, GPR_NUM> Stage::gprs;
std::array<int, V_NUM> Stage::vrs;
@@ -19,7 +26,7 @@ Response Stage::check_out(unsigned int &v)
{
Response r;
if (this->is_checked_out(v))
- r = STALLED;
+ r = BLOCKED;
else {
r = OK;
v = this->check_out_register(v);
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 13ab66a..bdea65a 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -6,4 +6,4 @@
WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }
-Response WB::advance(InstrDTO &i, Response p) { return OK; }
+Response WB::advance(InstrDTO &next_instr, Response p) { return OK; }