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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
bd
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Author
2025-04-17
Keep track of checked out in DTO to simplify wb cond logic (bug)
bd
2025-04-16
Fix instruction opcode numbering issue, use assembler's output
bd
2025-04-16
Partial fixes for changes in DRAM/Cache, including uncovered bug
bd
2025-04-15
Added pipeline to GUI
Siddarth-Suresh
2025-04-12
Delete some more storage-only files
bd
2025-04-11
Move storage to a separate git repository.
bd
2025-04-02
Last fix to demo program
bd
2025-04-01
Fix bug with decode pushing checked_out when delayed with RAW
bd
2025-04-01
GUI and controller on separate threads
Siddarth-Suresh
2025-03-29
Merge pull request #37 from bdunahu/bdunahu
Siddarth Suresh
Instr, InstrDTO gets/sets, other structures required for decode -- tests as we move forward -- base classes -- decode stage implemented
2025-03-29
Make UI Responsive
Siddarth-Suresh
2025-03-29
Layout changes
Siddarth-Suresh
2025-03-28
add get_instr_fields func to parse instruction fields from raw bits
bd
2025-03-24
Added gui folder with its own CMake to house GUI+main.cc
bd
