| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-03-30 | Setting condition code register, overflow guard | bd | |
| 2025-03-29 | get_instr_fields return mnemonic rather than opcode and type | bd | |
| 2025-03-28 | add get_instr_fields func to parse instruction fields from raw bits | bd | |
| 2025-03-22 | Add controller.h, implementation and tests. | bd | |
| 2025-03-11 | Fix small issue in fetch_resource wih off by one cycle count | bd | |
| 2025-03-11 | fix lots of bugs | bd | |
| 2025-03-11 | Clarify size of mem and cache in definitions, CLI print invalid tags | bd | |
| 2025-03-11 | cli display clock cycle, parse ';' delimited commands | bd | |
| 2025-03-10 | overload << operator for dram | bd | |
| 2025-03-10 | before error with catch crashing with global singleton logger | bd | |
| 2025-03-10 | Update cli method signatures, add some getters to cache and storage | bd | |
| 2025-03-09 | Improve documentation in definitions.h | bd | |
| 2025-03-08 | Add get_bit_fields, which parses cache fields from a memory address | bd | |
| 2025-03-06 | dram write (no delay, no accessor tracking | bd | |
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index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
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