| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-04-21 | add RET instruction | bd | |
| 2025-04-21 | Add licensing information | bd | |
| 2025-04-01 | Ensure all stages only do work if they are not 'OK' | bd | |
| 2025-03-31 | MEM WB stage | Siddarth-Suresh | |
| 2025-03-30 | Setting condition code register, overflow guard | bd | |
| 2025-03-29 | get_instr_fields return mnemonic rather than opcode and type | bd | |
| 2025-03-28 | Move get_instr_fields, add all instruction mnemonics | bd | |
| 2025-03-27 | Instr, InstrDTO gets/sets, other structures required for decode | bd | |
 |
index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
| summaryrefslogtreecommitdiff |