| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-04-21 | add RET instruction | bd | |
| 2025-04-21 | Add licensing information | bd | |
| 2025-04-16 | Fix instruction opcode numbering issue, use assembler's output | bd | |
| 2025-03-30 | Setting condition code register, overflow guard | bd | |
| 2025-03-29 | get_instr_fields return mnemonic rather than opcode and type | bd | |
| 2025-03-28 | Move get_instr_fields, add all instruction mnemonics | bd | |
| 2025-03-27 | Instr, InstrDTO gets/sets, other structures required for decode | bd | |
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index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
| summaryrefslogtreecommitdiff |