| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-04-01 | Finish adding initial tests for full pipeline | bd | |
| 2025-04-01 | Lots of fixes and tests | bd | |
| 2025-04-01 | Fix a lot of pipeline bugs | bd | |
| 2025-04-01 | Ensure all stages only do work if they are not 'OK' | bd | |
| 2025-03-31 | CR Comments | Siddarth-Suresh | |
| 2025-03-31 | MEM WB stage | Siddarth-Suresh | |
| 2025-03-29 | Fetch stage properly holds objects until parent is ready | bd | |
| 2025-03-29 | Add implementation functions for checking out a register. | bd | |
| 2025-03-27 | Use an unordered map to record pipe stage history on instructions | bd | |
| 2025-03-27 | Instr, InstrDTO gets/sets, other structures required for decode | bd | |
| 2025-03-26 | Add fetch stage implementation, tests, program loading, DTO object | bd | |
 |
index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
| summaryrefslogtreecommitdiff |