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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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storage
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Author
2025-03-09
cache store single test
bd
2025-03-09
initialize wait_time in dram to resolve undefined behavior
bd
2025-03-09
Untested implementation for loading absent data into cache
bd
2025-03-09
Move do_write to dram.h, is_blocked flag
bd
2025-03-09
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-09
Code review comments
Siddarth-Suresh
2025-03-09
Add bitset field to cache.h for keeping track of write/validity
bd
2025-03-09
Implement dram load
Siddarth-Suresh
2025-03-08
Properly initialize the requester
bd
2025-03-08
Remove queue in storage.h
bd
2025-03-08
Fix bug where wait_time would decrease while idle
bd
2025-03-08
enforce single unit per clock cycle, order to serve storage requests
bd
2025-03-08
Refactor function return scheme
bd
2025-03-06
Allow sidedoor free access to writing memory
bd
2025-03-06
dram implement delay and conflicting request logic
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
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2025-03-05
whitespace
bd
2025-03-05
constructors + method declarations for cache, dram, reponse, storage
bd
2025-03-04
Impartial storage/dram classes
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