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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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utils
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2025-04-12
Delete some more storage-only files
bd
2025-03-29
Add implementation functions for checking out a register.
bd
2025-03-28
Move get_instr_fields, add all instruction mnemonics
bd
2025-03-28
add get_instr_fields func to parse instruction fields from raw bits
bd
2025-03-27
Instr, InstrDTO gets/sets, other structures required for decode
bd
2025-03-21
Small cleanups to up a lot of inplementation details
bd
2025-03-11
fix lots of bugs
bd
2025-03-11
clarify macro names, implement load in CLI, fix many display issues
bd
2025-03-11
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-11
Tests for write line in Dram, memory address wrapping implementation and tests
Siddarth-Suresh
2025-03-11
Clarify size of mem and cache in definitions, CLI print invalid tags
bd
2025-03-11
cli display clock cycle, parse ';' delimited commands
bd
2025-03-10
CLI view, clock, store, program banner
bd
2025-03-09
Improve documentation in definitions.h
bd
2025-03-09
Add bitset field to cache.h for keeping track of write/validity
bd
2025-03-08
Add get_bit_fields, which parses cache fields from a memory address
bd
