| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 27 hours | Fix bug where vector registers were not cleared when length was 0 | bd | |
| 29 hours | Stride load, stride store | bd | |
| 36 hours | Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general | bd | |
| 37 hours | Remove I_VECT field types | bd | |
| 2 days | Fix bug where too many vector elements were written back | bd | |
| 2 days | Separate ex advance into methods handling different field types | bd | |
| 2 days | Rename load/store vector to i_vector | bd | |
| 2 days | Add type field to InstrDTO, required for next refactor | bd | |
| 4 days | Move is_logical_type and is_vector_type to instr.h | bd | |
| 2025-04-27 | WB and MEM changes for vectors | Siddarth-Suresh | |
| 2025-04-26 | Initial vector extension changes | Siddarth-Suresh | |
| 2025-04-22 | Remove 'type' field out of InstrDTO | bd | |
| 2025-04-22 | Use a struct for InstrDTO | bd | |
| 2025-04-22 | Remove subfolders | bd | |
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index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
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