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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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dram.cc
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2025-03-23
Merge pull request #30 from bdunahu/bdunahu
bd
Add controller.h, implementation and tests.
2025-03-22
Remove manual clock advancing / resolution from storage devices
bd
2025-03-22
Add controller.h, implementation and tests.
bd
2025-03-21
Rewrite current cache.cc tests, add test-helper function to dram
bd
2025-03-20
Rewrite all Dram tests to use Fixture
bd
2025-03-20
Make memory simulator an optional command, experiment with fixtures
bd
2025-03-11
Rename read/write to read_line and write_word
bd
2025-03-11
Tests for write line in Dram, memory address wrapping implementation and tests
Siddarth-Suresh
2025-03-11
support for reading word, writing line to storage, dirty cache eviction, ↵
Siddarth-Suresh
cache load
2025-03-11
Write line, dirty cache eviction, cache load word/line (for future ↵
Siddarth-Suresh
multilevel cache implementation)
2025-03-09
Cache object issues with uninitialized fields, another cache test
bd
2025-03-09
Code review comments
Siddarth-Suresh
2025-03-09
Implement dram load
Siddarth-Suresh
2025-03-08
Remove queue in storage.h
bd
2025-03-08
enforce single unit per clock cycle, order to serve storage requests
bd
2025-03-08
Refactor function return scheme
bd
2025-03-06
Allow sidedoor free access to writing memory
bd
2025-03-06
Fix a memory leak
bd
2025-03-06
dram implement delay and conflicting request logic
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
bd
2025-03-05
whitespace
bd
2025-03-05
constructors + method declarations for cache, dram, reponse, storage
bd
