| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-03-11 | fix lots of bugs | bd | |
| 2025-03-11 | clarify macro names, implement load in CLI, fix many display issues | bd | |
| 2025-03-11 | Tests for write line in Dram, memory address wrapping implementation and tests | Siddarth-Suresh | |
| 2025-03-08 | Add get_bit_fields, which parses cache fields from a memory address | bd | |
 |
index : RISC-VECTOR.git | |
| A simulator for the custom RISC-V[ECTOR] ISA written in C++ | bd |
| summaryrefslogtreecommitdiff |