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RISC-VECTOR.git
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A simulator for the custom RISC-V[ECTOR] ISA written in C++
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2025-03-09
Merge remote-tracking branch 'origin/master' into bdunahu
bd
2025-03-09
Code review comments
Siddarth-Suresh
2025-03-09
Implement dram load
Siddarth-Suresh
2025-03-08
Add get_bit_fields, which parses cache fields from a memory address
bd
2025-03-08
Remove queue in storage.h
bd
2025-03-08
enforce single unit per clock cycle, order to serve storage requests
bd
2025-03-08
Refactor function return scheme
bd
2025-03-06
Allow sidedoor free access to writing memory
bd
2025-03-06
Fix a memory leak
bd
2025-03-06
dram implement delay and conflicting request logic
bd
2025-03-06
dram write (no delay, no accessor tracking
bd
2025-03-06
Storage.view method, some initial tests
bd
2025-03-05
whitespace
bd
2025-03-05
constructors + method declarations for cache, dram, reponse, storage
bd
2025-03-02
Added logger class, tests, arg parsing and cleanup
bd
2025-03-01
windows environment fix, catch2 version change changes included
Siddarth-Suresh
2025-02-24
Add catch2 testing framework and integrate with CMake
bd
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