From a59c031ca0521bfb00bfc5f8f65af45c89804a37 Mon Sep 17 00:00:00 2001 From: bd Date: Tue, 11 Mar 2025 11:54:21 -0400 Subject: Clarify size of mem and cache in definitions, CLI print invalid tags --- inc/definitions.h | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'inc/definitions.h') diff --git a/inc/definitions.h b/inc/definitions.h index f015ce9..1d68a60 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -13,28 +13,27 @@ #define LINE_SIZE static_cast(pow(2, 2)) /** + * The number of bits to specify a memory word * The number of bits to specify a memory line - * calculated as: (/ (expt 2 15) 4) + * The total number of lines in memory */ -#define MEM_SPEC 8 -/** - * The total number of words in memory - */ -#define MEM_SIZE static_cast(pow(2, MEM_SPEC)) +#define MEM_WORD_SPEC 10 +#define MEM_LINE_SPEC static_cast(MEM_WORD_SPEC - LINE_SPEC) +#define MEM_LINES static_cast(pow(2, MEM_LINE_SPEC)) /** + * The number of bits to specify a l1 cache word * The number of bits to specify a l1 cache line + * The total number of lines in l1 cache */ -#define L1_CACHE_SPEC 5 -/** - * The total number of words in l1 cache - */ -#define L1_CACHE_SIZE static_cast(pow(2, L1_CACHE_SPEC)) +#define L1_CACHE_WORD_SPEC 7 +#define L1_CACHE_LINE_SPEC static_cast(L1_CACHE_WORD_SPEC - LINE_SPEC) +#define L1_CACHE_LINES static_cast(pow(2, L1_CACHE_LINE_SPEC)) /** * The total number of cycles a memory access takes. */ -#define MEM_DELAY 4 +#define MEM_DELAY 3 /** * The total number of cycles a level one cache access takes -- cgit v1.2.3