From eaa87e9fcd90c00d6261cbdb854efb7a09467f1d Mon Sep 17 00:00:00 2001 From: bd Date: Thu, 27 Mar 2025 20:30:18 -0400 Subject: Instr, InstrDTO gets/sets, other structures required for decode --- inc/stage.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'inc/stage.h') diff --git a/inc/stage.h b/inc/stage.h index ac810a9..04de475 100644 --- a/inc/stage.h +++ b/inc/stage.h @@ -4,6 +4,7 @@ #include "instrDTO.h" #include "response.h" #include "storage.h" +#include "accessor.h" #include class Stage @@ -26,14 +27,18 @@ class Stage virtual Response advance(InstrDTO &i) = 0; protected: + /** + * The name of the pipeline stage. + */ + Accessor id; /** * The shared pool of general-purpose integer registers. */ - static std::array gprs; + static std::array gprs; /** * The address of the currently executing instruction. */ - static int pc; + static unsigned int pc; /** * A pointer to the next stage in the pipeline. */ -- cgit v1.2.3 From bc47d9131869b1f072e21d9cb61746d14bf30751 Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 29 Mar 2025 02:36:38 -0400 Subject: get_instr_fields return mnemonic rather than opcode and type --- inc/definitions.h | 5 +++ inc/id.h | 33 +++++++++++++++---- inc/instr.h | 9 +++--- inc/stage.h | 4 +++ src/cli/cli.cc | 3 ++ src/sim/id.cc | 97 ++++++++++++++++++++++++++++++++----------------------- src/sim/instr.cc | 38 +++++++++++++--------- src/sim/stage.cc | 1 + tests/id.cc | 85 +++++++++++++++++++++--------------------------- 9 files changed, 160 insertions(+), 115 deletions(-) (limited to 'inc/stage.h') diff --git a/inc/definitions.h b/inc/definitions.h index c9367ff..3238a8b 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -51,6 +51,11 @@ */ #define GPR_NUM 16 +/** + * The number of vector registers + */ +#define V_NUM 8 + /** * The number of bits to specify an instruction type */ diff --git a/inc/id.h b/inc/id.h index 1503457..2411402 100644 --- a/inc/id.h +++ b/inc/id.h @@ -1,5 +1,6 @@ #ifndef ID_H #define ID_H +#include "instr.h" #include "instrDTO.h" #include "response.h" #include "stage.h" @@ -19,20 +20,38 @@ class ID : public Stage /** * Parse an instruction into a type, opcode, and fields. If the type is * invalid, only the type field will be set. + * + * This method is marked public so it may be tested, and is not used outside + * of this class during normal execution. + * * @param the resulting first field, which varies per type. To call this * function properly, this field must contain the full instruction bytes on * function entry. * @param the resulting second field, which varies per type. * @param the resulting third field, which varies per type. - * @param the resulting type. - * @param the resulting opcode. + * @param the resulting mnemonic. */ void get_instr_fields( - signed int &s1, - signed int &s2, - signed int &s3, - unsigned int &type, - unsigned int &opcode); + signed int &s1, signed int &s2, signed int &s3, Mnemonic &m); + + private: + /** + * Helper for `get_instr_fields`. + * Given a raw instruction, returns the mnemonic and type. + * This operation will destroy the original arguments. + * @param the raw bits to parse. + * @param the resulting mnemonic. + * @param the resulting type. + */ + void split_instr(signed int &raw, unsigned int &type, Mnemonic &m); + /** + * Facilitates checking out a register by dereferencing the register + specified by the first parameter. Registers that are checked out cannot be + checked out until they are checked in. + * @param + * @return the contents of the register. + */ + Response dereference_register(signed int &); }; #endif /* ID_D_INCLUDED */ diff --git a/inc/instr.h b/inc/instr.h index 98ecf1d..08b4fd0 100644 --- a/inc/instr.h +++ b/inc/instr.h @@ -2,7 +2,7 @@ #define INSTR_H #include #include -#include +#include enum Mnemonic { ADD, @@ -42,15 +42,14 @@ enum Mnemonic { BOF, PUSH, POP, + NOP, }; -std::ostream &operator<<(std::ostream &os, Mnemonic a); - namespace instr { // clang-format off - extern const std::map mnemonic_map; - extern const std::map> instr_map; + extern const std::unordered_map mnemonic_map; + extern const std::unordered_map> instr_map; // clang-format on } // namespace instr diff --git a/inc/stage.h b/inc/stage.h index 04de475..f6bad41 100644 --- a/inc/stage.h +++ b/inc/stage.h @@ -35,6 +35,10 @@ class Stage * The shared pool of general-purpose integer registers. */ static std::array gprs; + /** + * The shared pool of general-purpose vector registers. + */ + static std::array vrs; /** * The address of the currently executing instruction. */ diff --git a/src/cli/cli.cc b/src/cli/cli.cc index 022b266..58575cb 100644 --- a/src/cli/cli.cc +++ b/src/cli/cli.cc @@ -3,6 +3,7 @@ #include "definitions.h" #include "dram.h" #include "response.h" +#include "accessor.h" #include "utils.h" #include @@ -43,6 +44,7 @@ Cli::Cli() }; commands['r'] = [this](std::vector args) { + (void)args; reset(); return; }; @@ -61,6 +63,7 @@ Cli::Cli() }; commands['h'] = [this](std::vector args) { + (void)args; help(); return; }; diff --git a/src/sim/id.cc b/src/sim/id.cc index 65acef5..c6e42d5 100644 --- a/src/sim/id.cc +++ b/src/sim/id.cc @@ -1,5 +1,6 @@ #include "id.h" #include "accessor.h" +#include "instr.h" #include "instrDTO.h" #include "logger.h" #include "response.h" @@ -12,54 +13,70 @@ ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; } Response ID::advance(InstrDTO &i) { Response r; } +// TODO this function is ugly void ID::get_instr_fields( - signed int &s1, - signed int &s2, - signed int &s3, - unsigned int &type, - unsigned int &opcode) + signed int &s1, signed int &s2, signed int &s3, Mnemonic &m) { - // unsigned int &opcode; - int opcode_bits; - - type = GET_LS_BITS(s1, TYPE_SIZE); - opcode_bits = (type == 0b0) ? R_OPCODE_SIZE : OPCODE_SIZE; + unsigned int type, s0b, s1b, s2b; + this->split_instr(s1, type, m); + // define the parsing bounds + s0b = REG_SIZE; switch (type) { - case 0: + case 0b00: // R-TYPE - opcode += GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits); - s3 = GET_MID_BITS( - s1, TYPE_SIZE + opcode_bits + (REG_SIZE * 2), - TYPE_SIZE + opcode_bits + (REG_SIZE * 3)); - s2 = GET_MID_BITS( - s1, TYPE_SIZE + opcode_bits + REG_SIZE, - TYPE_SIZE + opcode_bits + (REG_SIZE * 2)); - s1 = GET_MID_BITS( - s1, TYPE_SIZE + opcode_bits, - TYPE_SIZE + opcode_bits + REG_SIZE); + s1b = s0b + REG_SIZE; + s2b = s1b + REG_SIZE; break; - case 1: + case 0b01: // I-TYPE - opcode = GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits); - s3 = GET_MID_BITS( - s1, TYPE_SIZE + opcode_bits + (REG_SIZE * 2), WORD_SPEC); - s2 = GET_MID_BITS( - s1, TYPE_SIZE + opcode_bits + REG_SIZE, - TYPE_SIZE + opcode_bits + (REG_SIZE * 2)); - s1 = GET_MID_BITS( - s1, TYPE_SIZE + opcode_bits, TYPE_SIZE + opcode_bits + REG_SIZE); + s1b = s0b + REG_SIZE; + s2b = WORD_SPEC; break; - case 2: + case 0b10: // J-TYPE - opcode = GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits); - s2 = GET_MID_BITS(s1, TYPE_SIZE + OPCODE_SIZE + REG_SIZE, WORD_SPEC); - s1 = GET_MID_BITS( - s1, TYPE_SIZE + OPCODE_SIZE, TYPE_SIZE + OPCODE_SIZE + REG_SIZE); - break; - default: - global_log->log( - DEBUG, - string_format("%s returning invalid type: %d", __FUNCTION__, type)); + s1b = WORD_SPEC; } + + if (type != 0b10) + s3 = GET_MID_BITS(s1, s1b, s2b); + + s2 = GET_MID_BITS(s1, s0b, s1b); + s1 = GET_LS_BITS(s1, s0b); +} + +void ID::split_instr(signed int &raw, unsigned int &type, Mnemonic &m) +{ + unsigned int opcode, opcode_size; + + type = GET_LS_BITS(raw, TYPE_SIZE); + opcode_size = (type == 0b0) ? R_OPCODE_SIZE : OPCODE_SIZE; + opcode = GET_MID_BITS(raw, TYPE_SIZE, TYPE_SIZE + opcode_size); + try { + m = instr::mnemonic_map.at((opcode << 2) + type); + } catch (std::out_of_range const &) { + m = NOP; + } + + raw = (unsigned int)raw >> (TYPE_SIZE + opcode_size); +} + +Response ID::dereference_register(signed int &v) +{ + Response r; + r = OK; + + if (v < 0 || v >= GPR_NUM + V_NUM) { + global_log->log( + ERROR, string_format( + "instruction tried to access register %d, which does " + "not exist", + v)); + exit(EXIT_FAILURE); + } else if (v >= GPR_NUM) + v = this->vrs[v % GPR_NUM]; + else + v = this->gprs[v]; + + return r; } diff --git a/src/sim/instr.cc b/src/sim/instr.cc index 50aa71d..08edf5e 100644 --- a/src/sim/instr.cc +++ b/src/sim/instr.cc @@ -1,6 +1,7 @@ #include "instr.h" #include #include +#include // clang-format off #define INIT_INSTRUCTION(mnemonic, body) \ @@ -12,7 +13,7 @@ namespace instr { // clang-format off -const std::map> +const std::unordered_map> // clang-format on instr_map = { @@ -20,26 +21,33 @@ const std::map mnemonic_map = { - {0b0000100, ADD}, {0b0001000, SUB}, {0b0001100, MUL}, {0b0010000, QUOT}, - {0b0010100, REM}, {0b0011000, SFTR}, {0b0011100, SFTL}, {0b0100000, AND}, - {0b0100100, OR}, {0b0101000, NOT}, {0b0101100, XOR}, {0b0110000, ADDV}, - {0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV}, {0b1000000, CMP}, - {0b1000100, CEV}, {0b000101, LOAD}, {0b001001, LOADV}, {0b001101, ADDI}, - {0b010001, SUBI}, {0b010101, SFTRI}, {0b011101, SFTLI}, {0b100001, ANDI}, - {0b100101, ORI}, {0b101001, XORI}, {0b101101, STORE}, {0b110001, STOREV}, - {0b000101, CEV}, {0b000101, LOAD}, {0b001001, LOADV}, {0b001001, LOADV}, - {0b000110, JMP}, {0b001010, JRL}, {0b001110, JAL}, {0b010010, BEQ}, - {0b010110, BGT}, {0b011010, BUF}, {0b011110, BOF}, {0b100010, PUSH}, - {0b100110, POP}, +const std::unordered_map mnemonic_map = { + {0b0000100, ADD}, {0b0001000, SUB}, {0b0001100, MUL}, + {0b0010000, QUOT}, {0b0010100, REM}, {0b0011000, SFTR}, + {0b0011100, SFTL}, {0b0100000, AND}, {0b0100100, OR}, + {0b0101000, NOT}, {0b0101100, XOR}, {0b0110000, ADDV}, + {0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV}, + {0b1000000, CMP}, {0b1000100, CEV}, {0b000101, LOAD}, + {0b001001, LOADV}, {0b0001101, ADDI}, {0b0010001, SUBI}, + {0b0010101, SFTRI}, {0b0011101, SFTLI}, {0b0100001, ANDI}, + {0b0100101, ORI}, {0b0101001, XORI}, {0b0101101, STORE}, + {0b0110001, STOREV}, {0b0000101, CEV}, {0b0000101, LOAD}, + {0b0001001, LOADV}, {0b0001001, LOADV}, {0b0000110, JMP}, + {0b0001010, JRL}, {0b0001110, JAL}, {0b0010010, BEQ}, + {0b0010110, BGT}, {0b0011010, BUF}, {0b0011110, BOF}, + {0b0100010, PUSH}, {0b0100110, POP}, }; } // namespace instr diff --git a/src/sim/stage.cc b/src/sim/stage.cc index 6599298..560cc41 100644 --- a/src/sim/stage.cc +++ b/src/sim/stage.cc @@ -5,6 +5,7 @@ Stage::Stage(Stage *next) { } std::array Stage::gprs; +std::array Stage::vrs; unsigned int Stage::pc; Storage *Stage::storage; bool Stage::is_pipelined; diff --git a/tests/id.cc b/tests/id.cc index e09276f..b847026 100644 --- a/tests/id.cc +++ b/tests/id.cc @@ -4,6 +4,7 @@ #include "dram.h" #include "if.h" #include "instrDTO.h" +#include "instr.h" #include class IDPipeFixture @@ -49,110 +50,98 @@ class IDPipeFixture Controller *ct; }; -TEST_CASE_METHOD(IDPipeFixture, "Parse invalid type", "[utils]") +TEST_CASE_METHOD(IDPipeFixture, "Parse invalid type", "[id]") { signed int s1 = 0, s2 = 0, s3 = 0; - unsigned int type = 0, opcode = 0; + Mnemonic m; s1 = 0x00FF00FF; - this->d->get_instr_fields(s1, s2, s3, type, opcode); - - REQUIRE(type == 0b11); - // behavior does nothing - CHECK(s1 == 0x00FF00FF); - CHECK(s2 == 0b0); - CHECK(s3 == 0b0); - CHECK(opcode == 0b0); + this->d->get_instr_fields(s1, s2, s3, m); + CHECK(m == NOP); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary r-type # one", "[utils]") +TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary r-type # one", "[id]") { signed int s1 = 0, s2 = 0, s3 = 0; - unsigned int type = 0, opcode = 0; + Mnemonic m; - s1 = 0xCCCCCCCC; - this->d->get_instr_fields(s1, s2, s3, type, opcode); + s1 = 0xCCCCCC0C; + this->d->get_instr_fields(s1, s2, s3, m); - REQUIRE(type == 0b00); - CHECK(s1 == 0b11001); + CHECK(s1 == 0b11000); CHECK(s2 == 0b01100); CHECK(s3 == 0b00110); - CHECK(opcode == 0b10011); + CHECK(m == MUL); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary r-type # two", "[utils]") +TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary r-type # two", "[id]") { signed int s1 = 0, s2 = 0, s3 = 0; - unsigned int type = 0, opcode = 0; + Mnemonic m; - s1 = 0x99AABBCC; - this->d->get_instr_fields(s1, s2, s3, type, opcode); + s1 = 0x99AABB0C; + this->d->get_instr_fields(s1, s2, s3, m); - REQUIRE(type == 0b00); - CHECK(s1 == 0b10111); + CHECK(s1 == 0b10110); CHECK(s2 == 0b01011); CHECK(s3 == 0b10101); - CHECK(opcode == 0b10011); + CHECK(m == MUL); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary i-type # one", "[utils]") +TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary i-type # one", "[id]") { signed int s1 = 0, s2 = 0, s3 = 0; - unsigned int type = 0, opcode = 0; + Mnemonic m; s1 = 0xDDDDDDDD; - this->d->get_instr_fields(s1, s2, s3, type, opcode); + this->d->get_instr_fields(s1, s2, s3, m); - REQUIRE(type == 0b01); CHECK(s1 == 0b10111); CHECK(s2 == 0b11011); CHECK(s3 == 0xDDDD); - CHECK(opcode == 0b0111); + CHECK(m == SFTLI); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary i-type # two", "[utils]") +TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary i-type # two", "[id]") { signed int s1 = 0, s2 = 0, s3 = 0; - unsigned int type = 0, opcode = 0; + Mnemonic m; s1 = 0xAABBCCDD; - this->d->get_instr_fields(s1, s2, s3, type, opcode); + this->d->get_instr_fields(s1, s2, s3, m); - REQUIRE(type == 0b01); CHECK(s1 == 0b10011); CHECK(s2 == 0b11001); CHECK(s3 == 0xAABB); - CHECK(opcode == 0b0111); + CHECK(m == SFTLI); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary j-type # one", "[utils]") +TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary j-type # one", "[id]") { signed int s1 = 0, s2 = 0, s3 = 0; - unsigned int type = 0, opcode = 0; + Mnemonic m; - s1 = 0xEEEEEEEE; - this->d->get_instr_fields(s1, s2, s3, type, opcode); + s1 = 0xEEEEEE1E; + this->d->get_instr_fields(s1, s2, s3, m); - REQUIRE(type == 0b10); - CHECK(s1 == 0b11011); + CHECK(s1 == 0b11000); CHECK(s2 == 0b111011101110111011101); - CHECK(opcode == 0b1011); + CHECK(m == BOF); // behavior does nothing CHECK(s3 == 0b0); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary j-type # two", "[utils]") +TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary j-type # two", "[id]") { signed int s1 = 0, s2 = 0, s3 = 0; - unsigned int type = 0, opcode = 0; + Mnemonic m; - s1 = 0xBBCCDDEE; - this->d->get_instr_fields(s1, s2, s3, type, opcode); + s1 = 0xBBCCDD0E; + this->d->get_instr_fields(s1, s2, s3, m); - REQUIRE(type == 0b10); - CHECK(s1 == 0b10111); + CHECK(s1 == 0b10100); CHECK(s2 == 0b101110111100110011011); - CHECK(opcode == 0b1011); + CHECK(m == JAL); // behavior does nothing CHECK(s3 == 0b0); } -- cgit v1.2.3 From 9793bf119cc6314e264bdfc9e98bc27c81db0adb Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 29 Mar 2025 12:30:54 -0400 Subject: Add implementation functions for checking out a register. --- inc/instrDTO.h | 21 ++++++++++++-------- inc/response.h | 1 + inc/stage.h | 40 +++++++++++++++++++++++++++++++++++++- src/sim/id.cc | 37 ++++++++++++----------------------- src/sim/instrDTO.cc | 4 ++++ src/sim/stage.cc | 53 ++++++++++++++++++++++++++++++++++++++++++++++++--- src/utils/response.cc | 2 +- 7 files changed, 120 insertions(+), 38 deletions(-) (limited to 'inc/stage.h') diff --git a/inc/instrDTO.h b/inc/instrDTO.h index 2a6ab1f..77a223e 100644 --- a/inc/instrDTO.h +++ b/inc/instrDTO.h @@ -1,9 +1,10 @@ #ifndef INSTRDTO_H #define INSTRDTO_H -#include +#include "accessor.h" +#include "instr.h" #include +#include #include -#include "accessor.h" class InstrDTO { @@ -39,9 +40,9 @@ class InstrDTO */ signed int get_s3(); /** - * @return the string representation of oper. + * @return the mnemonic of the instruction */ - std::string get_oper_name(); + Mnemonic get_mnemonic(); /** * @param set hist key @@ -63,6 +64,10 @@ class InstrDTO * @param s3 */ void set_s3(signed int); + /** + * @param the mnemonic of the instruction + */ + void set_mnemonic(Mnemonic); private: /** @@ -82,10 +87,10 @@ class InstrDTO signed int s1; signed int s2; signed int s3; - /** - * The operation to be conducted during the execute phase. - */ - std::function instr; + /** + * The mnemonic of the operation. + */ + Mnemonic mnemonic; }; #endif /* INSTRDTO_H_INCLUDED */ diff --git a/inc/response.h b/inc/response.h index 6cd6678..05e9352 100644 --- a/inc/response.h +++ b/inc/response.h @@ -6,6 +6,7 @@ enum Response { OK, WAIT, BLOCKED, + STALLED, }; std::ostream &operator<<(std::ostream &os, Response r); diff --git a/inc/stage.h b/inc/stage.h index f6bad41..0348263 100644 --- a/inc/stage.h +++ b/inc/stage.h @@ -1,11 +1,12 @@ #ifndef STAGE_H #define STAGE_H +#include "accessor.h" #include "definitions.h" #include "instrDTO.h" #include "response.h" #include "storage.h" -#include "accessor.h" #include +#include class Stage { @@ -27,6 +28,16 @@ class Stage virtual Response advance(InstrDTO &i) = 0; protected: + /** + * Facilitates register checkout. + * It does this by checking that the register passed in is not currently + * checked out. If true, then replaces r with the value of the register and + * returns OK. If false, returns STALLED. + * + * @param the registers number, to be dereferenced. + * @return OK if `r` is not checked out, STALLED otherwise. + */ + Response check_out(unsigned int &r); /** * The name of the pipeline stage. */ @@ -59,6 +70,33 @@ class Stage * The current clock cycle. */ static int clock_cycle; + + private: + /** + * Helper for `check_out`. + * Returns true if r are not checked out, false otherwise. + * @param a list of register numbers. + * @return true if registers are not in checked_out, false otherwise. + */ + bool is_checked_out(unsigned int r); + /** + * Helper for `check_out`. + * Checks out a single register, and places it in checked_out. + * @param a register number. + * @return the value in the register. + */ + signed int check_out_register(unsigned int r); + // TODO fix this comment after writeback stage + /** + * Helper for `check_out_register` + * @param the register number. + * @return the value in the associated register. + */ + signed int dereference_register(unsigned int r); + /** + * The set of registers currently checked out. + */ + static std::set checked_out; }; #endif /* STAGE_H_INCLUDED */ diff --git a/src/sim/id.cc b/src/sim/id.cc index c6e42d5..e9c48df 100644 --- a/src/sim/id.cc +++ b/src/sim/id.cc @@ -5,13 +5,20 @@ #include "logger.h" #include "response.h" #include "stage.h" -#include "utils.h" - -static Logger *global_log = Logger::getInstance(); ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; } -Response ID::advance(InstrDTO &i) { Response r; } +Response ID::advance(InstrDTO &i) +{ + Response r; + signed int s1, s2, s3; + Mnemonic m; + + s1 = i.get_instr_bits(); + + get_instr_fields(s1, s2, s3, m); + return r; +} // TODO this function is ugly void ID::get_instr_fields( @@ -53,30 +60,10 @@ void ID::split_instr(signed int &raw, unsigned int &type, Mnemonic &m) opcode_size = (type == 0b0) ? R_OPCODE_SIZE : OPCODE_SIZE; opcode = GET_MID_BITS(raw, TYPE_SIZE, TYPE_SIZE + opcode_size); try { - m = instr::mnemonic_map.at((opcode << 2) + type); + m = instr::mnemonic_map.at((opcode << TYPE_SIZE) + type); } catch (std::out_of_range const &) { m = NOP; } raw = (unsigned int)raw >> (TYPE_SIZE + opcode_size); } - -Response ID::dereference_register(signed int &v) -{ - Response r; - r = OK; - - if (v < 0 || v >= GPR_NUM + V_NUM) { - global_log->log( - ERROR, string_format( - "instruction tried to access register %d, which does " - "not exist", - v)); - exit(EXIT_FAILURE); - } else if (v >= GPR_NUM) - v = this->vrs[v % GPR_NUM]; - else - v = this->gprs[v]; - - return r; -} diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc index 7864eb4..7418033 100644 --- a/src/sim/instrDTO.cc +++ b/src/sim/instrDTO.cc @@ -19,6 +19,8 @@ signed int InstrDTO::get_s2() { return this->s2; } signed int InstrDTO::get_s3() { return this->s3; } +Mnemonic InstrDTO::get_mnemonic() { return this->mnemonic; } + void InstrDTO::set_time_of(Accessor a, int i) { this->hist[a] = i; } void InstrDTO::set_instr_bits(signed int instr) { this->instr_bits = instr; } @@ -28,3 +30,5 @@ void InstrDTO::set_s1(signed int s) { this->s1 = s; } void InstrDTO::set_s2(signed int s) { this->s2 = s; } void InstrDTO::set_s3(signed int s) { this->s3 = s; } + +void InstrDTO::set_mnemonic(Mnemonic m) { this->mnemonic = m; } diff --git a/src/sim/stage.cc b/src/sim/stage.cc index 560cc41..8d9dfc0 100644 --- a/src/sim/stage.cc +++ b/src/sim/stage.cc @@ -1,12 +1,59 @@ #include "stage.h" +#include "utils.h" +#include +#include -Stage::Stage(Stage *next) { - this->next = next; -} +static Logger *global_log = Logger::getInstance(); + +Stage::Stage(Stage *next) { this->next = next; } std::array Stage::gprs; std::array Stage::vrs; +std::set Stage::checked_out; unsigned int Stage::pc; Storage *Stage::storage; bool Stage::is_pipelined; int Stage::clock_cycle; + +Response Stage::check_out(unsigned int &v) +{ + Response r; + if (this->is_checked_out(v)) + r = STALLED; + else { + r = OK; + v = this->check_out_register(v); + } + return r; +} + +bool Stage::is_checked_out(unsigned int r) +{ + return this->checked_out.find(r) != this->checked_out.end(); +} + +signed int Stage::check_out_register(unsigned int v) +{ + signed int r; + this->checked_out.insert(v); + + r = this->dereference_register(v); + return r; +} + +signed int Stage::dereference_register(unsigned int v) +{ + signed int r; + + if (v >= GPR_NUM + V_NUM) { + global_log->log( + ERROR, string_format( + "instruction tried to access register %d, which does " + "not exist", + v)); + exit(EXIT_FAILURE); + } + + r = (v >= GPR_NUM) ? this->vrs[v % GPR_NUM] : this->gprs[v]; + return r; +} diff --git a/src/utils/response.cc b/src/utils/response.cc index def6578..3d6e439 100644 --- a/src/utils/response.cc +++ b/src/utils/response.cc @@ -3,6 +3,6 @@ std::ostream &operator<<(std::ostream &os, Response r) { - const std::string nameR[] = {"OK", "WAIT", "BLOCKED"}; + const std::string nameR[] = {"OK", "WAIT", "BLOCKED", "STALLED"}; return os << nameR[r]; } -- cgit v1.2.3 From ac0ae7206491a42cdba70560b0db41cfc8c7f642 Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 29 Mar 2025 12:58:14 -0400 Subject: Add parameter to Stage::advance so status can transfer down the pipe --- inc/controller.h | 2 +- inc/ex.h | 2 +- inc/id.h | 2 +- inc/if.h | 2 +- inc/mm.h | 2 +- inc/stage.h | 6 ++++-- inc/wb.h | 2 +- src/sim/controller.cc | 6 +++--- src/sim/ex.cc | 2 +- src/sim/id.cc | 2 +- src/sim/if.cc | 2 +- src/sim/mm.cc | 2 +- src/sim/wb.cc | 2 +- tests/if.cc | 6 +++--- 14 files changed, 21 insertions(+), 19 deletions(-) (limited to 'inc/stage.h') diff --git a/inc/controller.h b/inc/controller.h index 4b102ce..ac83a78 100644 --- a/inc/controller.h +++ b/inc/controller.h @@ -36,7 +36,7 @@ class Controller : public Stage * @return the pc. */ int get_pc(); - Response advance(InstrDTO &i) override; + Response advance(InstrDTO &i, Response p) override; }; #endif /* CONTROLLER_H_INCLUDED */ diff --git a/inc/ex.h b/inc/ex.h index fef411a..c7b7663 100644 --- a/inc/ex.h +++ b/inc/ex.h @@ -14,7 +14,7 @@ class EX : public Stage */ EX(Stage *next); - Response advance(InstrDTO &i) override; + Response advance(InstrDTO &i, Response p) override; }; #endif /* EX_H_INCLUDED */ diff --git a/inc/id.h b/inc/id.h index 2411402..95dde37 100644 --- a/inc/id.h +++ b/inc/id.h @@ -15,7 +15,7 @@ class ID : public Stage */ ID(Stage *next); - Response advance(InstrDTO &i) override; + Response advance(InstrDTO &i, Response p) override; /** * Parse an instruction into a type, opcode, and fields. If the type is diff --git a/inc/if.h b/inc/if.h index 7906c22..a6869f7 100644 --- a/inc/if.h +++ b/inc/if.h @@ -15,7 +15,7 @@ class IF : public Stage */ IF(Stage *next); - Response advance(InstrDTO &i) override; + Response advance(InstrDTO &i, Response p) override; }; #endif /* IF_H_INCLUDED */ diff --git a/inc/mm.h b/inc/mm.h index 90ebe5a..edee589 100644 --- a/inc/mm.h +++ b/inc/mm.h @@ -14,7 +14,7 @@ class MM : public Stage */ MM(Stage *next); - Response advance(InstrDTO &i) override; + Response advance(InstrDTO &i, Response p) override; }; #endif /* MM_H_INCLUDED */ diff --git a/inc/stage.h b/inc/stage.h index 0348263..761b9f6 100644 --- a/inc/stage.h +++ b/inc/stage.h @@ -22,10 +22,12 @@ class Stage * Advances this stage by a single clock cycle. * @param a DTO object containing various information about an instruction * moving through the pipeline. - * @return a response, indicating whether this pipeline stage is stalled, + * @param a response, indicating whether or not the parent pipe stage is + * busy. + * @return a response, indicating whether this pipeline stage is stalling, * busy, or done. */ - virtual Response advance(InstrDTO &i) = 0; + virtual Response advance(InstrDTO &i, Response p) = 0; protected: /** diff --git a/inc/wb.h b/inc/wb.h index b8f5d8f..c1a6a32 100644 --- a/inc/wb.h +++ b/inc/wb.h @@ -14,7 +14,7 @@ class WB : public Stage */ WB(Stage *next); - Response advance(InstrDTO &i) override; + Response advance(InstrDTO &i, Response p) override; }; #endif /* WB_H_INCLUDED */ diff --git a/src/sim/controller.cc b/src/sim/controller.cc index 45aa9a0..833d900 100644 --- a/src/sim/controller.cc +++ b/src/sim/controller.cc @@ -19,7 +19,7 @@ void Controller::run_for(int number) InstrDTO instr; int i; for (i = 0; i < number; ++i) { - this->advance(instr); + this->advance(instr, OK); } } @@ -29,11 +29,11 @@ std::array Controller::get_gprs() { return this->gprs; } int Controller::get_pc() { return this->pc; } -Response Controller::advance(InstrDTO &i) +Response Controller::advance(InstrDTO &i, Response p) { Response r; - r = this->next->advance(i); + r = this->next->advance(i, p); ++this->clock_cycle; return r; } diff --git a/src/sim/ex.cc b/src/sim/ex.cc index 46f5417..c9c2116 100644 --- a/src/sim/ex.cc +++ b/src/sim/ex.cc @@ -6,4 +6,4 @@ EX::EX(Stage *stage) : Stage(stage) { this->id = EXEC; } -Response EX::advance(InstrDTO &i) { return OK; } +Response EX::advance(InstrDTO &i, Response p) { return OK; } diff --git a/src/sim/id.cc b/src/sim/id.cc index e9c48df..70fab9a 100644 --- a/src/sim/id.cc +++ b/src/sim/id.cc @@ -8,7 +8,7 @@ ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; } -Response ID::advance(InstrDTO &i) +Response ID::advance(InstrDTO &i, Response p) { Response r; signed int s1, s2, s3; diff --git a/src/sim/if.cc b/src/sim/if.cc index 559ad2e..099ff1c 100644 --- a/src/sim/if.cc +++ b/src/sim/if.cc @@ -6,7 +6,7 @@ IF::IF(Stage *stage) : Stage(stage) { this->id = FETCH; } -Response IF::advance(InstrDTO &i) +Response IF::advance(InstrDTO &i, Response p) { Response r; signed int bits; diff --git a/src/sim/mm.cc b/src/sim/mm.cc index c5357f9..93c5b87 100644 --- a/src/sim/mm.cc +++ b/src/sim/mm.cc @@ -6,7 +6,7 @@ MM::MM(Stage *stage) : Stage(stage) { this->id = MEM; } -Response MM::advance(InstrDTO &i) +Response MM::advance(InstrDTO &i, Response p) { return OK; } diff --git a/src/sim/wb.cc b/src/sim/wb.cc index 218ed9a..13ab66a 100644 --- a/src/sim/wb.cc +++ b/src/sim/wb.cc @@ -6,4 +6,4 @@ WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; } -Response WB::advance(InstrDTO &i) { return OK; } +Response WB::advance(InstrDTO &i, Response p) { return OK; } diff --git a/tests/if.cc b/tests/if.cc index 3e68ac4..3be3305 100644 --- a/tests/if.cc +++ b/tests/if.cc @@ -36,7 +36,7 @@ class IFPipeFixture Response r; for (i = 0; i < this->m_delay + 1; ++i) { - r = this->ct->advance(instr); + r = this->ct->advance(instr, OK); // check response CHECK(r == BLOCKED); } @@ -52,11 +52,11 @@ class IFPipeFixture Response r; for (i = 0; i < this->c_delay; ++i) { - r = this->ct->advance(instr); + r = this->ct->advance(instr, OK); // check response CHECK(r == WAIT); } - r = this->ct->advance(instr); + r = this->ct->advance(instr, OK); // check response CHECK(r == OK); } -- cgit v1.2.3 From d21a1a9caa1f1791343a5376121936e552b1124c Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 29 Mar 2025 17:11:17 -0400 Subject: Fetch stage properly holds objects until parent is ready --- inc/ex.h | 2 +- inc/id.h | 2 +- inc/if.h | 12 +++++++++++- inc/mm.h | 2 +- inc/stage.h | 26 +++++++++++++++++--------- inc/wb.h | 2 +- src/sim/controller.cc | 4 ++-- src/sim/ex.cc | 2 +- src/sim/id.cc | 11 ++++++----- src/sim/if.cc | 30 ++++++++++++++++++++++-------- src/sim/instrDTO.cc | 1 + src/sim/mm.cc | 2 +- src/sim/stage.cc | 11 +++++++++-- src/sim/wb.cc | 2 +- tests/if.cc | 34 ++++++++++++++++++++++++++++++++-- 15 files changed, 107 insertions(+), 36 deletions(-) (limited to 'inc/stage.h') diff --git a/inc/ex.h b/inc/ex.h index c7b7663..e67980d 100644 --- a/inc/ex.h +++ b/inc/ex.h @@ -14,7 +14,7 @@ class EX : public Stage */ EX(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; }; #endif /* EX_H_INCLUDED */ diff --git a/inc/id.h b/inc/id.h index 95dde37..34e1a47 100644 --- a/inc/id.h +++ b/inc/id.h @@ -15,7 +15,7 @@ class ID : public Stage */ ID(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; /** * Parse an instruction into a type, opcode, and fields. If the type is diff --git a/inc/if.h b/inc/if.h index a6869f7..9f84e51 100644 --- a/inc/if.h +++ b/inc/if.h @@ -15,7 +15,17 @@ class IF : public Stage */ IF(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; + + private: + /** + * Performs a fetch only if a current fetch is not pending. Pending means + * that a fetch has completed successfully, but the caller stage in the + * pipeline is not ready to receive it. In this case, `curr_instr` is not + * the nullptr. + * @return STALLED if we are waiting on the storage devices, OK otherwise. + */ + void fetch_with_buffer(); }; #endif /* IF_H_INCLUDED */ diff --git a/inc/mm.h b/inc/mm.h index edee589..0d2ce82 100644 --- a/inc/mm.h +++ b/inc/mm.h @@ -14,7 +14,7 @@ class MM : public Stage */ MM(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; }; #endif /* MM_H_INCLUDED */ diff --git a/inc/stage.h b/inc/stage.h index 761b9f6..ff4455b 100644 --- a/inc/stage.h +++ b/inc/stage.h @@ -7,6 +7,7 @@ #include "storage.h" #include #include +#include class Stage { @@ -17,17 +18,16 @@ class Stage * @return A newly allocated stage object. */ Stage(Stage *next); - virtual ~Stage() = default; + virtual ~Stage(); /** * Advances this stage by a single clock cycle. - * @param a DTO object containing various information about an instruction - * moving through the pipeline. + * @param a DTO object containing the next instruction to be processed. * @param a response, indicating whether or not the parent pipe stage is - * busy. + * ready to accept a new instruction object next cycle. * @return a response, indicating whether this pipeline stage is stalling, * busy, or done. */ - virtual Response advance(InstrDTO &i, Response p) = 0; + virtual Response advance(InstrDTO &next_instr, Response p) = 0; protected: /** @@ -56,10 +56,6 @@ class Stage * The address of the currently executing instruction. */ static unsigned int pc; - /** - * A pointer to the next stage in the pipeline. - */ - Stage *next; /** * A pointer to the top-level storage device. */ @@ -72,6 +68,18 @@ class Stage * The current clock cycle. */ static int clock_cycle; + /** + * A pointer to the next stage in the pipeline. + */ + Stage *next; + /** + * A pointer to the current instruction this stage is processing. + */ + std::unique_ptr curr_instr; + /** + * The current status of this stage. + */ + Response status; private: /** diff --git a/inc/wb.h b/inc/wb.h index c1a6a32..9a708a6 100644 --- a/inc/wb.h +++ b/inc/wb.h @@ -14,7 +14,7 @@ class WB : public Stage */ WB(Stage *next); - Response advance(InstrDTO &i, Response p) override; + Response advance(InstrDTO &next_instr, Response p) override; }; #endif /* WB_H_INCLUDED */ diff --git a/src/sim/controller.cc b/src/sim/controller.cc index 833d900..17937eb 100644 --- a/src/sim/controller.cc +++ b/src/sim/controller.cc @@ -29,11 +29,11 @@ std::array Controller::get_gprs() { return this->gprs; } int Controller::get_pc() { return this->pc; } -Response Controller::advance(InstrDTO &i, Response p) +Response Controller::advance(InstrDTO &next_instr, Response p) { Response r; - r = this->next->advance(i, p); + r = this->next->advance(next_instr, p); ++this->clock_cycle; return r; } diff --git a/src/sim/ex.cc b/src/sim/ex.cc index c9c2116..5b561f8 100644 --- a/src/sim/ex.cc +++ b/src/sim/ex.cc @@ -6,4 +6,4 @@ EX::EX(Stage *stage) : Stage(stage) { this->id = EXEC; } -Response EX::advance(InstrDTO &i, Response p) { return OK; } +Response EX::advance(InstrDTO &next_instr, Response p) { return OK; } diff --git a/src/sim/id.cc b/src/sim/id.cc index 70fab9a..83a8751 100644 --- a/src/sim/id.cc +++ b/src/sim/id.cc @@ -8,15 +8,16 @@ ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; } -Response ID::advance(InstrDTO &i, Response p) +Response ID::advance(InstrDTO &next_instr, Response p) { Response r; - signed int s1, s2, s3; - Mnemonic m; + r = OK; + // signed int s1, s2, s3; + // Mnemonic m; - s1 = i.get_instr_bits(); + // s1 = next_instr.get_instr_bits(); - get_instr_fields(s1, s2, s3, m); + // get_instr_fields(s1, s2, s3, m); return r; } diff --git a/src/sim/if.cc b/src/sim/if.cc index 099ff1c..de044f8 100644 --- a/src/sim/if.cc +++ b/src/sim/if.cc @@ -6,17 +6,31 @@ IF::IF(Stage *stage) : Stage(stage) { this->id = FETCH; } -Response IF::advance(InstrDTO &i, Response p) +Response IF::advance(InstrDTO &next_instr, Response p) +{ + this->fetch_with_buffer(); + if (this->status == OK && p == OK) { + // mutual consent + ++this->pc; + this->curr_instr->set_time_of(this->id, this->clock_cycle); + next_instr = *this->curr_instr; + curr_instr = nullptr; + } + return this->status; +} + +void IF::fetch_with_buffer() { Response r; signed int bits; - r = this->storage->read_word(this->id, this->pc, bits); - if (r == OK) { - ++this->pc; - i.set_time_of(this->id, this->clock_cycle); - i.set_instr_bits(bits); + if (this->curr_instr == nullptr) { + r = this->storage->read_word(this->id, this->pc, bits); + if (r == OK) { + this->status = r; + this->curr_instr = std::make_unique(); + this->curr_instr->set_instr_bits(bits); + } else + this->status = STALLED; } - - return r; } diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc index 7418033..5a7fe3b 100644 --- a/src/sim/instrDTO.cc +++ b/src/sim/instrDTO.cc @@ -7,6 +7,7 @@ InstrDTO::InstrDTO() this->s1 = 0; this->s2 = 0; this->s3 = 0; + this->mnemonic = NOP; } int InstrDTO::get_time_of(Accessor a) { return this->hist[a]; } diff --git a/src/sim/mm.cc b/src/sim/mm.cc index 93c5b87..f394420 100644 --- a/src/sim/mm.cc +++ b/src/sim/mm.cc @@ -6,7 +6,7 @@ MM::MM(Stage *stage) : Stage(stage) { this->id = MEM; } -Response MM::advance(InstrDTO &i, Response p) +Response MM::advance(InstrDTO &next_instr, Response p) { return OK; } diff --git a/src/sim/stage.cc b/src/sim/stage.cc index 8d9dfc0..48ee494 100644 --- a/src/sim/stage.cc +++ b/src/sim/stage.cc @@ -5,7 +5,14 @@ static Logger *global_log = Logger::getInstance(); -Stage::Stage(Stage *next) { this->next = next; } +Stage::Stage(Stage *next) +{ + this->next = next; + this->curr_instr = nullptr; + this->status = OK; +} + +Stage::~Stage() { delete this->next; }; std::array Stage::gprs; std::array Stage::vrs; @@ -19,7 +26,7 @@ Response Stage::check_out(unsigned int &v) { Response r; if (this->is_checked_out(v)) - r = STALLED; + r = BLOCKED; else { r = OK; v = this->check_out_register(v); diff --git a/src/sim/wb.cc b/src/sim/wb.cc index 13ab66a..bdea65a 100644 --- a/src/sim/wb.cc +++ b/src/sim/wb.cc @@ -6,4 +6,4 @@ WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; } -Response WB::advance(InstrDTO &i, Response p) { return OK; } +Response WB::advance(InstrDTO &next_instr, Response p) { return OK; } diff --git a/tests/if.cc b/tests/if.cc index 3be3305..bb25afa 100644 --- a/tests/if.cc +++ b/tests/if.cc @@ -38,7 +38,7 @@ class IFPipeFixture for (i = 0; i < this->m_delay + 1; ++i) { r = this->ct->advance(instr, OK); // check response - CHECK(r == BLOCKED); + CHECK(r == STALLED); } this->fetch_cache(instr); } @@ -54,7 +54,7 @@ class IFPipeFixture for (i = 0; i < this->c_delay; ++i) { r = this->ct->advance(instr, OK); // check response - CHECK(r == WAIT); + CHECK(r == STALLED); } r = this->ct->advance(instr, OK); // check response @@ -98,3 +98,33 @@ TEST_CASE_METHOD(IFPipeFixture, "fetch returns two instuctions", "[if_pipe]") CHECK(instr.get_time_of(FETCH) == expected_cycles); REQUIRE(instr.get_instr_bits() == this->p[1]); } + +TEST_CASE_METHOD(IFPipeFixture, "fetch waits with old instruction", "[if_pipe]") +{ + Response r; + InstrDTO instr; + int i, expected_cycles, fetch_cycles; + + fetch_cycles = this->m_delay + this->c_delay + 2; + expected_cycles = this->m_delay + (this->c_delay * 2) + 1; + + for (i = 0; i < this->m_delay + 1; ++i) { + r = this->ct->advance(instr, BLOCKED); + // check response + CHECK(r == STALLED); + } + for (i = 0; i < this->c_delay; ++i) { + r = this->ct->advance(instr, BLOCKED); + // check response + CHECK(r == STALLED); + } + for (i = 0; i < expected_cycles - fetch_cycles; ++i) { + r = this->ct->advance(instr, BLOCKED); + // check response + CHECK(r == OK); + } + + r = this->ct->advance(instr, OK); + CHECK(instr.get_time_of(FETCH) == expected_cycles); + REQUIRE(instr.get_instr_bits() == this->p[0]); +} -- cgit v1.2.3 From 6bce0485a0f9ce92bc235f063a1f9aab2d59a1c9 Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 29 Mar 2025 19:45:21 -0400 Subject: Add proper read and write guard methods, clean up id test file --- inc/id.h | 45 ++++++++++++---- inc/stage.h | 53 +++++++------------ src/sim/id.cc | 95 ++++++++++++++++++++++++++-------- src/sim/stage.cc | 52 +++++-------------- tests/id.cc | 153 ++++++++++++++++++++++++++++++++----------------------- 5 files changed, 228 insertions(+), 170 deletions(-) (limited to 'inc/stage.h') diff --git a/inc/id.h b/inc/id.h index 34e1a47..f8c167d 100644 --- a/inc/id.h +++ b/inc/id.h @@ -34,7 +34,42 @@ class ID : public Stage void get_instr_fields( signed int &s1, signed int &s2, signed int &s3, Mnemonic &m); + /* The following methods are made public so that they may be tested, and are + * not to be called from outside classes during standard execution. + */ + + /** + * Facilitates register checkout and data hazard management. + * It does this by checking that the register passed in is not currently + * checked out. If true, then replaces r with the value of the register and + * returns OK. If false, returns STALLED. + * + * @param the registers number, to be dereferenced. + * @return OK if `r` is not checked out, STALLED otherwise. + */ + Response read_guard(signed int &r); + /** + * Facilitates register checkout and data hazard management. + * Checks out a register and returns it. + * + * @param the registers number, to be dereferenced and checked out. + */ + void write_guard(signed int &r); + private: + // TODO write me + /** + * Helper for `` + * Attempts to parse and dereference instruction arguments. If a desc + + * @param the resulting first field. To call this function properly, this + * field must contain the section of the instruction to be parsed. + * @param the resulting second field. + * @param the resulting third field. + */ + void decode_R_type(signed int &s1, signed int &s2, signed int &s3); + void decode_I_type(signed int &s1, signed int &s2, signed int &s3); + void decode_J_type(signed int &s1, signed int &s2); /** * Helper for `get_instr_fields`. * Given a raw instruction, returns the mnemonic and type. @@ -44,14 +79,6 @@ class ID : public Stage * @param the resulting type. */ void split_instr(signed int &raw, unsigned int &type, Mnemonic &m); - /** - * Facilitates checking out a register by dereferencing the register - specified by the first parameter. Registers that are checked out cannot be - checked out until they are checked in. - * @param - * @return the contents of the register. - */ - Response dereference_register(signed int &); }; -#endif /* ID_D_INCLUDED */ +#endif /* ID_H_INCLUDED */ diff --git a/inc/stage.h b/inc/stage.h index ff4455b..19e3896 100644 --- a/inc/stage.h +++ b/inc/stage.h @@ -6,7 +6,7 @@ #include "response.h" #include "storage.h" #include -#include +#include #include class Stage @@ -31,15 +31,18 @@ class Stage protected: /** - * Facilitates register checkout. - * It does this by checking that the register passed in is not currently - * checked out. If true, then replaces r with the value of the register and - * returns OK. If false, returns STALLED. - * - * @param the registers number, to be dereferenced. - * @return OK if `r` is not checked out, STALLED otherwise. + * Helper for `check_out`. + * Returns true if r are not checked out, false otherwise. + * @param a list of register numbers. + * @return true if registers are not in checked_out, false otherwise. + */ + bool is_checked_out(signed int r); + /** + * Returns the value of the register corresponding to `v`. + * @param the register number. + * @return the value in the associated register. */ - Response check_out(unsigned int &r); + signed int dereference_register(signed int v); /** * The name of the pipeline stage. */ @@ -68,6 +71,11 @@ class Stage * The current clock cycle. */ static int clock_cycle; + // TODO fix this comment after writeback stage + /** + * The set of registers currently checked out. + */ + static std::deque checked_out; /** * A pointer to the next stage in the pipeline. */ @@ -80,33 +88,6 @@ class Stage * The current status of this stage. */ Response status; - - private: - /** - * Helper for `check_out`. - * Returns true if r are not checked out, false otherwise. - * @param a list of register numbers. - * @return true if registers are not in checked_out, false otherwise. - */ - bool is_checked_out(unsigned int r); - /** - * Helper for `check_out`. - * Checks out a single register, and places it in checked_out. - * @param a register number. - * @return the value in the register. - */ - signed int check_out_register(unsigned int r); - // TODO fix this comment after writeback stage - /** - * Helper for `check_out_register` - * @param the register number. - * @return the value in the associated register. - */ - signed int dereference_register(unsigned int r); - /** - * The set of registers currently checked out. - */ - static std::set checked_out; }; #endif /* STAGE_H_INCLUDED */ diff --git a/src/sim/id.cc b/src/sim/id.cc index 83a8751..c04b31f 100644 --- a/src/sim/id.cc +++ b/src/sim/id.cc @@ -5,52 +5,85 @@ #include "logger.h" #include "response.h" #include "stage.h" +#include ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; } Response ID::advance(InstrDTO &next_instr, Response p) { Response r; - r = OK; - // signed int s1, s2, s3; - // Mnemonic m; + signed int s1, s2, s3; + Mnemonic m; - // s1 = next_instr.get_instr_bits(); + s1 = next_instr.get_instr_bits(); - // get_instr_fields(s1, s2, s3, m); + get_instr_fields(s1, s2, s3, m); return r; } +void ID::decode_R_type(signed int &s1, signed int &s2, signed int &s3) +{ + unsigned int s0b, s1b, s2b; + Response r1, r2; + + s0b = REG_SIZE; + s1b = s0b + REG_SIZE; + s2b = s1b + REG_SIZE; + s3 = GET_MID_BITS(s1, s1b, s2b); + s2 = GET_MID_BITS(s1, s0b, s1b); + s1 = GET_LS_BITS(s1, s0b); + + r1 = this->read_guard(s1); + r2 = this->read_guard(s2); + this->write_guard(s3); + + this->status = std::max(r1, r2); +} +void ID::decode_I_type(signed int &s1, signed int &s2, signed int &s3) +{ + unsigned int s0b, s1b, s2b; + + s0b = REG_SIZE; + s1b = s0b + REG_SIZE; + s2b = WORD_SPEC; + s3 = GET_MID_BITS(s1, s1b, s2b); + s2 = GET_MID_BITS(s1, s0b, s1b); + s1 = GET_LS_BITS(s1, s0b); + + this->status = this->read_guard(s1); + this->write_guard(s2); +} + +void ID::decode_J_type(signed int &s1, signed int &s2) +{ + unsigned int s0b, s1b; + + s0b = REG_SIZE; + s1b = WORD_SPEC; + s2 = GET_MID_BITS(s1, s0b, s1b); + s1 = GET_LS_BITS(s1, s0b); + + this->status = this->read_guard(*&s1); +} + // TODO this function is ugly void ID::get_instr_fields( signed int &s1, signed int &s2, signed int &s3, Mnemonic &m) { - unsigned int type, s0b, s1b, s2b; + unsigned int type; this->split_instr(s1, type, m); - // define the parsing bounds - s0b = REG_SIZE; switch (type) { case 0b00: - // R-TYPE - s1b = s0b + REG_SIZE; - s2b = s1b + REG_SIZE; + this->decode_R_type(s1, s2, s3); break; case 0b01: - // I-TYPE - s1b = s0b + REG_SIZE; - s2b = WORD_SPEC; + this->decode_I_type(s1, s2, s3); break; case 0b10: - // J-TYPE - s1b = WORD_SPEC; + this->decode_J_type(s1, s2); + break; } - - if (type != 0b10) - s3 = GET_MID_BITS(s1, s1b, s2b); - - s2 = GET_MID_BITS(s1, s0b, s1b); - s1 = GET_LS_BITS(s1, s0b); } void ID::split_instr(signed int &raw, unsigned int &type, Mnemonic &m) @@ -68,3 +101,21 @@ void ID::split_instr(signed int &raw, unsigned int &type, Mnemonic &m) raw = (unsigned int)raw >> (TYPE_SIZE + opcode_size); } + +Response ID::read_guard(signed int &v) +{ + Response r; + if (this->is_checked_out(v)) + r = BLOCKED; + else { + r = OK; + v = this->dereference_register(v); + } + return r; +} + +void ID::write_guard(signed int &v) +{ + this->checked_out.push_back(v); + v = this->dereference_register(v); +} diff --git a/src/sim/stage.cc b/src/sim/stage.cc index 48ee494..a8f3f9e 100644 --- a/src/sim/stage.cc +++ b/src/sim/stage.cc @@ -1,9 +1,7 @@ #include "stage.h" #include "utils.h" #include -#include - -static Logger *global_log = Logger::getInstance(); +#include Stage::Stage(Stage *next) { @@ -16,51 +14,29 @@ Stage::~Stage() { delete this->next; }; std::array Stage::gprs; std::array Stage::vrs; -std::set Stage::checked_out; +std::deque Stage::checked_out; unsigned int Stage::pc; Storage *Stage::storage; bool Stage::is_pipelined; int Stage::clock_cycle; -Response Stage::check_out(unsigned int &v) -{ - Response r; - if (this->is_checked_out(v)) - r = BLOCKED; - else { - r = OK; - v = this->check_out_register(v); - } - return r; -} - -bool Stage::is_checked_out(unsigned int r) -{ - return this->checked_out.find(r) != this->checked_out.end(); -} - -signed int Stage::check_out_register(unsigned int v) +signed int Stage::dereference_register(signed int v) { signed int r; - this->checked_out.insert(v); - r = this->dereference_register(v); - return r; -} - -signed int Stage::dereference_register(unsigned int v) -{ - signed int r; - - if (v >= GPR_NUM + V_NUM) { - global_log->log( - ERROR, string_format( - "instruction tried to access register %d, which does " - "not exist", - v)); - exit(EXIT_FAILURE); + if (v < 0 || v >= GPR_NUM + V_NUM) { + throw std::out_of_range(string_format( + "instruction tried to access register %d, which does " + "not exist", + v)); } r = (v >= GPR_NUM) ? this->vrs[v % GPR_NUM] : this->gprs[v]; return r; } + +bool Stage::is_checked_out(signed int r) +{ + return std::find(this->checked_out.begin(), this->checked_out.end(), r) != + this->checked_out.end(); +} diff --git a/tests/id.cc b/tests/id.cc index b847026..f500b07 100644 --- a/tests/id.cc +++ b/tests/id.cc @@ -3,145 +3,168 @@ #include "controller.h" #include "dram.h" #include "if.h" -#include "instrDTO.h" #include "instr.h" +#include "instrDTO.h" #include -class IDPipeFixture +class IDFixture { public: - IDPipeFixture() + IDFixture() { Dram *dr; - dr = new Dram(this->m_delay); - // 0xC00 is a nop - p = {0xC000, 0xC001, 0xC002, 0xC003}; - dr->load(p); - - this->c = new Cache(dr, this->c_delay); + dr = new Dram(3); + this->c = new Cache(dr, 1); IF *f = new IF(nullptr); this->d = new ID(f); this->ct = new Controller(this->d, this->c, true); }; - ~IDPipeFixture() + ~IDFixture() { delete this->ct; delete this->c; }; - - // /** - // * Requests something to do until it is received. - // */ - // void fetch(InstrDTO &instr) - // { - // Response r = WAIT; - - // while (r != OK) { - // r = this->ct->advance(instr); - // } - // } - - int m_delay = 3; - int c_delay = 1; + signed int encode_R_type( + signed int s3, + signed int s2, + signed int s1, + signed int opcode, + signed int type) + { + signed int t; + t = s3; + t = (t << REG_SIZE) + s2; + t = (t << REG_SIZE) + s1; + t = (t << R_OPCODE_SIZE) + opcode; + t = (t << TYPE_SIZE) + type; + return t; + } + signed int encode_I_type( + signed int s3, + signed int s2, + signed int s1, + signed int opcode, + signed int type) + { + signed int t; + t = s3; + t = (t << REG_SIZE) + s2; + t = (t << REG_SIZE) + s1; + t = (t << OPCODE_SIZE) + opcode; + t = (t << TYPE_SIZE) + type; + return t; + } + signed int encode_J_type( + signed int s2, signed int s1, signed int opcode, signed int type) + { + signed int t; + t = s2; + t = (t << REG_SIZE) + s1; + t = (t << OPCODE_SIZE) + opcode; + t = (t << TYPE_SIZE) + type; + return t; + } std::vector p; Cache *c; ID *d; Controller *ct; }; -TEST_CASE_METHOD(IDPipeFixture, "Parse invalid type", "[id]") +TEST_CASE_METHOD(IDFixture, "Parse invalid type", "[id]") { signed int s1 = 0, s2 = 0, s3 = 0; Mnemonic m; - s1 = 0x00FF00FF; + s1 = 0xFFFFFFFF; this->d->get_instr_fields(s1, s2, s3, m); CHECK(m == NOP); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary r-type # one", "[id]") +TEST_CASE_METHOD(IDFixture, "Parse arbitrary r-type # one", "[id]") { - signed int s1 = 0, s2 = 0, s3 = 0; + signed int s1 = -1, s2 = -1, s3 = -1; Mnemonic m; - s1 = 0xCCCCCC0C; + s1 = this->encode_R_type(0b0, 0b1, 0b10, 0b11, 0b0); this->d->get_instr_fields(s1, s2, s3, m); - CHECK(s1 == 0b11000); - CHECK(s2 == 0b01100); - CHECK(s3 == 0b00110); + CHECK(s1 == 0x00000000); // registers are empty + CHECK(s2 == 0x00000000); + CHECK(s3 == 0x00000000); CHECK(m == MUL); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary r-type # two", "[id]") +TEST_CASE_METHOD(IDFixture, "Parse arbitrary r-type # two", "[id]") { - signed int s1 = 0, s2 = 0, s3 = 0; + signed int s1 = -1, s2 = -1, s3 = -1; Mnemonic m; - s1 = 0x99AABB0C; + s1 = this->encode_R_type(0b10000, 0b01000, 0b00100, 0b10, 0b0); this->d->get_instr_fields(s1, s2, s3, m); - CHECK(s1 == 0b10110); - CHECK(s2 == 0b01011); - CHECK(s3 == 0b10101); - CHECK(m == MUL); + CHECK(s1 == 0x00000000); // registers are empty + CHECK(s2 == 0b00000000); + CHECK(s3 == 0b00000000); + CHECK(m == SUB); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary i-type # one", "[id]") +TEST_CASE_METHOD(IDFixture, "Parse arbitrary i-type # one", "[id]") { - signed int s1 = 0, s2 = 0, s3 = 0; + signed int s1 = -1, s2 = -1, s3 = -1; Mnemonic m; - s1 = 0xDDDDDDDD; + s1 = this->encode_I_type(0xF, 0b1, 0b10, 0b0111, 0b1); this->d->get_instr_fields(s1, s2, s3, m); - CHECK(s1 == 0b10111); - CHECK(s2 == 0b11011); - CHECK(s3 == 0xDDDD); + CHECK(s1 == 0x00000000); // registers are empty + CHECK(s2 == 0x00000000); + CHECK(s3 == 0xF); CHECK(m == SFTLI); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary i-type # two", "[id]") +TEST_CASE_METHOD(IDFixture, "Parse arbitrary i-type # two", "[id]") { - signed int s1 = 0, s2 = 0, s3 = 0; + signed int s1 = -1, s2 = -1, s3 = -1; Mnemonic m; - s1 = 0xAABBCCDD; + s1 = this->encode_I_type(0xCC, 0b010, 0b101, 0b1011, 0b1); this->d->get_instr_fields(s1, s2, s3, m); - CHECK(s1 == 0b10011); - CHECK(s2 == 0b11001); - CHECK(s3 == 0xAABB); - CHECK(m == SFTLI); + CHECK(s1 == 0x00000000); // registers are empty + CHECK(s2 == 0x00000000); + CHECK(s3 == 0xCC); + CHECK(m == STORE); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary j-type # one", "[id]") +TEST_CASE_METHOD(IDFixture, "Parse arbitrary j-type # one", "[id]") { - signed int s1 = 0, s2 = 0, s3 = 0; + signed int s1 = -1, s2 = -1, s3 = -1; Mnemonic m; - s1 = 0xEEEEEE1E; + s1 = this->encode_J_type(0x3456, 0b10101, 0b0111, 0b10); this->d->get_instr_fields(s1, s2, s3, m); - CHECK(s1 == 0b11000); - CHECK(s2 == 0b111011101110111011101); + CHECK(s1 == 0x00000000); // registers are empty + CHECK(s2 == 0x3456); CHECK(m == BOF); // behavior does nothing - CHECK(s3 == 0b0); + CHECK(s3 == -1); } -TEST_CASE_METHOD(IDPipeFixture, "Parse arbitrary j-type # two", "[id]") +TEST_CASE_METHOD(IDFixture, "Parse arbitrary j-type # two", "[id]") { - signed int s1 = 0, s2 = 0, s3 = 0; + signed int s1 = -1, s2 = -1, s3 = -1; Mnemonic m; - s1 = 0xBBCCDD0E; + s1 = this->encode_J_type(0xBBCCF, 0b10101, 0b0011, 0b10); this->d->get_instr_fields(s1, s2, s3, m); - CHECK(s1 == 0b10100); - CHECK(s2 == 0b101110111100110011011); + CHECK(s1 == 0x00000000); // registers are empty + CHECK(s2 == 0xBBCCF); CHECK(m == JAL); // behavior does nothing - CHECK(s3 == 0b0); + CHECK(s3 == -1); } + +// TEST_CASE_METHOD(IDFixture, "No data hazards", "[id]") { signed int } -- cgit v1.2.3