From a59c031ca0521bfb00bfc5f8f65af45c89804a37 Mon Sep 17 00:00:00 2001 From: bd Date: Tue, 11 Mar 2025 11:54:21 -0400 Subject: Clarify size of mem and cache in definitions, CLI print invalid tags --- inc/cache.h | 4 ++-- inc/definitions.h | 23 +++++++++++------------ 2 files changed, 13 insertions(+), 14 deletions(-) (limited to 'inc') diff --git a/inc/cache.h b/inc/cache.h index 04f6181..a566f24 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -31,7 +31,7 @@ class Cache : public Storage * TODO this doesn't seem like good object-oriented practice. * @return this->meta */ - std::array, L1_CACHE_SIZE> get_meta() const; + std::array, L1_CACHE_LINES> get_meta() const; private: /** @@ -47,7 +47,7 @@ class Cache : public Storage * element in `data` is invalid. If the most second value of an element * is nonzero, the corresponding element in `data` is dirty. */ - std::array, L1_CACHE_SIZE> meta; + std::array, L1_CACHE_LINES> meta; }; std::ostream &operator<<(std::ostream &os, const Cache &c); diff --git a/inc/definitions.h b/inc/definitions.h index f015ce9..1d68a60 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -13,28 +13,27 @@ #define LINE_SIZE static_cast(pow(2, 2)) /** + * The number of bits to specify a memory word * The number of bits to specify a memory line - * calculated as: (/ (expt 2 15) 4) + * The total number of lines in memory */ -#define MEM_SPEC 8 -/** - * The total number of words in memory - */ -#define MEM_SIZE static_cast(pow(2, MEM_SPEC)) +#define MEM_WORD_SPEC 10 +#define MEM_LINE_SPEC static_cast(MEM_WORD_SPEC - LINE_SPEC) +#define MEM_LINES static_cast(pow(2, MEM_LINE_SPEC)) /** + * The number of bits to specify a l1 cache word * The number of bits to specify a l1 cache line + * The total number of lines in l1 cache */ -#define L1_CACHE_SPEC 5 -/** - * The total number of words in l1 cache - */ -#define L1_CACHE_SIZE static_cast(pow(2, L1_CACHE_SPEC)) +#define L1_CACHE_WORD_SPEC 7 +#define L1_CACHE_LINE_SPEC static_cast(L1_CACHE_WORD_SPEC - LINE_SPEC) +#define L1_CACHE_LINES static_cast(pow(2, L1_CACHE_LINE_SPEC)) /** * The total number of cycles a memory access takes. */ -#define MEM_DELAY 4 +#define MEM_DELAY 3 /** * The total number of cycles a level one cache access takes -- cgit v1.2.3 From f3d6ceaa6f0d716a4b0d30c5c8b27c74c55b96ac Mon Sep 17 00:00:00 2001 From: bd Date: Tue, 11 Mar 2025 19:02:55 -0400 Subject: fix lots of bugs --- inc/definitions.h | 1 + src/storage/cache.cc | 10 ++++++---- src/utils/utils.cc | 7 +++---- tests/utils.cc | 22 +++++++++++----------- 4 files changed, 21 insertions(+), 19 deletions(-) (limited to 'inc') diff --git a/inc/definitions.h b/inc/definitions.h index 1d68a60..80fccbe 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -19,6 +19,7 @@ */ #define MEM_WORD_SPEC 10 #define MEM_LINE_SPEC static_cast(MEM_WORD_SPEC - LINE_SPEC) +#define MEM_WORDS static_cast(pow(2, MEM_WORD_SPEC)) #define MEM_LINES static_cast(pow(2, MEM_LINE_SPEC)) /** diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 14a6e61..ea90f50 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -138,6 +138,7 @@ void Cache::fetch_resource(int expected) (meta->at(0) << (L1_CACHE_LINE_SPEC + LINE_SPEC)))); if (r == OK) { meta->at(1) = -1; + r = WAIT; } } else { r = this->lower->read_line(L1CACHE, expected, actual); @@ -165,11 +166,12 @@ std::ostream &operator<<(std::ostream &os, const Cache &c) std::vector> data = c.view(0, L1_CACHE_LINES); std::array, L1_CACHE_LINES> meta = c.get_meta(); + std::cout << "FOO " << meta.at(31)[0]; os << " " << std::setfill(' ') << std::setw(L1_CACHE_LINE_SPEC + 2) << "INDEX" << " | " << std::setfill(' ') << std::setw((8 + 3) * 4 - 1) << "DATA" << " | " << std::setfill(' ') - << std::setw(MEM_LINE_SPEC - LINE_SPEC - L1_CACHE_LINE_SPEC + 2) << "TAG" + << std::setw(MEM_LINE_SPEC - L1_CACHE_LINE_SPEC + 2) << "TAG" << " | D" << std::endl; for (int i = 0; i < L1_CACHE_LINES; ++i) { os << " 0b" << std::setw(L1_CACHE_LINE_SPEC) << std::bitset(i) @@ -178,12 +180,12 @@ std::ostream &operator<<(std::ostream &os, const Cache &c) os << "0x" << std::setfill('0') << std::setw(8) << std::hex << data.at(i).at(j) << " "; } - os << "| 0x" << std::setfill(' '); + os << "| 0b" << std::setfill(' '); if (meta.at(i)[0] < 0) - os << "?"; + os << std::setfill('?') << std::setw(MEM_LINE_SPEC - L1_CACHE_LINE_SPEC) << ""; else - os << std::bitset(meta.at(i)[0]); + os << std::bitset(meta.at(i)[0]); os << " | " << (int)(meta.at(i)[0] >= 0) << std::endl; } diff --git a/src/utils/utils.cc b/src/utils/utils.cc index 87ce488..ebbc1e9 100644 --- a/src/utils/utils.cc +++ b/src/utils/utils.cc @@ -7,8 +7,7 @@ void get_bit_fields(int address, int *tag, int *index, int *offset) { *tag = GET_MID_BITS( - address, LINE_SPEC + L1_CACHE_LINE_SPEC, - MEM_LINE_SPEC + LINE_SPEC + L1_CACHE_LINE_SPEC); + address, L1_CACHE_LINE_SPEC + LINE_SPEC, MEM_WORD_SPEC); *index = GET_MID_BITS(address, LINE_SPEC, L1_CACHE_LINE_SPEC + LINE_SPEC); *offset = GET_LS_BITS(address, LINE_SPEC); } @@ -31,7 +30,7 @@ const std::string string_format(const char *const zcFormat, ...) int wrap_address(int address) { if (address < 0){ - return ((address % MEM_LINES) + MEM_LINES) % MEM_LINES; + return ((address % MEM_WORDS) + MEM_WORDS) % MEM_WORDS; } - return address % MEM_LINES; + return address % MEM_WORDS; } diff --git a/tests/utils.cc b/tests/utils.cc index 900db1a..ea1a1ed 100644 --- a/tests/utils.cc +++ b/tests/utils.cc @@ -5,9 +5,9 @@ TEST_CASE("Parse arbitrary fields # one", "[cache]") { int tag, index, offset; - int address = 0b111110001010101; + int address = 0b0001010101; get_bit_fields(address, &tag, &index, &offset); - CHECK(tag == 0b11111000); + CHECK(tag == 0b000); CHECK(index == 0b10101); CHECK(offset == 0b01); } @@ -15,30 +15,30 @@ TEST_CASE("Parse arbitrary fields # one", "[cache]") TEST_CASE("Parse arbitrary fields # two", "[cache]") { int tag, index, offset; - int address = 0b000110100111011; + int address = 0b0100111011; get_bit_fields(address, &tag, &index, &offset); - CHECK(tag == 0b00011010); + CHECK(tag == 0b010); CHECK(index == 0b01110); CHECK(offset == 0b11); } TEST_CASE("wrap address outside upper bound", "[utils]") { - int address = MEM_LINES + 25; + int address = MEM_WORDS + 25; int wrapped = wrap_address(address); REQUIRE(wrapped == 25); } TEST_CASE("wrap address inside upper bound", "[utils]") { - int address = MEM_LINES - 25; + int address = MEM_WORDS - 25; int wrapped = wrap_address(address); - REQUIRE(wrapped == MEM_LINES - 25); + REQUIRE(wrapped == MEM_WORDS - 25); } TEST_CASE("wrap address at upper bound", "[utils]") { - int address = MEM_LINES; + int address = MEM_WORDS; int wrapped = wrap_address(address); REQUIRE(wrapped == 0); } @@ -47,14 +47,14 @@ TEST_CASE("wrap address lower than 0 with magnitude lesser than mem size", "[uti { int address = -10; int wrapped = wrap_address(address); - REQUIRE(wrapped == MEM_LINES - 10); + REQUIRE(wrapped == MEM_WORDS - 10); } TEST_CASE("wrap address lower than 0 but with magnitude greater than mem size", "[utils]") { - int address = -(MEM_LINES + 10); + int address = -(MEM_WORDS + 10); int wrapped = wrap_address(address); - REQUIRE(wrapped == MEM_LINES - 10); + REQUIRE(wrapped == MEM_WORDS - 10); } TEST_CASE("wrap address at 0", "[utils]") -- cgit v1.2.3 From 7c828204a091330eca7dd6495f02f54c2c0a3091 Mon Sep 17 00:00:00 2001 From: bd Date: Tue, 11 Mar 2025 20:26:59 -0400 Subject: Fix small issue in fetch_resource wih off by one cycle count --- inc/definitions.h | 2 +- src/storage/cache.cc | 11 ++++++----- 2 files changed, 7 insertions(+), 6 deletions(-) (limited to 'inc') diff --git a/inc/definitions.h b/inc/definitions.h index 80fccbe..eced554 100644 --- a/inc/definitions.h +++ b/inc/definitions.h @@ -39,7 +39,7 @@ /** * The total number of cycles a level one cache access takes */ -#define L1_CACHE_DELAY 1 +#define L1_CACHE_DELAY 0 /** * Return the N least-significant bits from integer K using a bit mask diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 4842ed5..3e2a5e0 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -119,6 +119,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data) void Cache::fetch_resource(int expected) { Response r = OK; + Response q; int tag, index, offset; std::array *actual; std::array *meta; @@ -128,21 +129,21 @@ void Cache::fetch_resource(int expected) actual = &this->data->at(index); if (meta->at(0) != tag) { + r = WAIT; // address not in cache if (meta->at(1) >= 0) { // occupant is dirty // writing line to DRam in case of dirty cache eviction - r = this->lower->write_line( + q = this->lower->write_line( L1CACHE, *actual, ((index << LINE_SPEC) + (meta->at(0) << (L1_CACHE_LINE_SPEC + LINE_SPEC)))); - if (r == OK) { + if (q == OK) { meta->at(1) = -1; - r = WAIT; } } else { - r = this->lower->read_line(L1CACHE, expected, *actual); - if (r == OK) { + q = this->lower->read_line(L1CACHE, expected, *actual); + if (q == OK) { meta->at(0) = tag; } } -- cgit v1.2.3