From 7aaa516c0de444c956dff88342a57e9313a19e34 Mon Sep 17 00:00:00 2001
From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>
Date: Sun, 27 Apr 2025 15:04:25 -0400
Subject: WB and MEM changes for vectors

---
 src/ex.cc | 39 +++++++++++++++++++++------------------
 1 file changed, 21 insertions(+), 18 deletions(-)

(limited to 'src/ex.cc')

diff --git a/src/ex.cc b/src/ex.cc
index 947407a..03a4e59 100644
--- a/src/ex.cc
+++ b/src/ex.cc
@@ -33,29 +33,26 @@ void EX::advance_helper()
 	Mnemonic m;
 
 	m = this->curr_instr->mnemonic;
+	pc = this->curr_instr->slot_B;
 
 	if(this->is_vector_type(m)) {
-		v1 = this->curr_instr->operands.vector.slot_one;
-		v2 = this->curr_instr->operands.vector.slot_two;
-		v3 = this->curr_instr->operands.vector.slot_three;
-		v_len = this->curr_instr->slot_A;
-		if(this->curr_instr->slot_C){
-			v_immediate = this->curr_instr->slot_C;
-		}
-		if(this->curr_instr->slot_B){
-			v_base_addr = this->curr_instr->slot_B;
+		if(this->curr_instr->mnemonic != LOADV && this->curr_instr->mnemonic != STOREV){
+			v1 = this->curr_instr->operands.vector.slot_one;
+			v2 = this->curr_instr->operands.vector.slot_two;
+			v3 = this->curr_instr->operands.vector.slot_three;	
+		} else {
+			v_immediate = this->curr_instr->operands.load_store_vector.immediate;
+			v_base_addr = this->curr_instr->operands.load_store_vector.base_addr;
 		}
-		/*if(v_len == 0){
-			//clear vector reg
+		v_len = this->curr_instr->slot_A;
+		if(v_len == 0){
+			//clear destination vector reg
 			v1.fill(0);
-			v2.fill(0);
-			v3.fill(0);
-		}*/	 
+		}	 
 	} else{
 		s1 = this->curr_instr->operands.integer.slot_one;
 		s2 = this->curr_instr->operands.integer.slot_two;
 		s3 = this->curr_instr->operands.integer.slot_three;
-		pc = this->curr_instr->slot_B;
 	}
 
 	if(this->is_logical(m)) {
@@ -216,12 +213,18 @@ void EX::advance_helper()
 			}
 			break;
 		case CEV:
-			bool equal = true;
-			for(int i=0;i<v_len;i++){
+			int i;
+			for(i=0;i<v_len;i++){
 				if(v1[i] != v2[i]){
-					equal = false;
+					break;
 				}
 			}
+			if(i == v_len){
+				this->set_condition(EQ, true);
+			} else {
+				this->set_condition(EQ, false);
+			}
+			break;
 		case LOADV:
 		case STOREV:
 			v_base_addr = v_base_addr + v_immediate;
-- 
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