From 43588597069587f6846a7d64a1957435bec5429d Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Sun, 11 May 2025 22:04:46 -0400
Subject: Add ROTV instruction

---
 src/id.cc | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

(limited to 'src/id.cc')

diff --git a/src/id.cc b/src/id.cc
index 9547486..58bde6b 100644
--- a/src/id.cc
+++ b/src/id.cc
@@ -99,25 +99,29 @@ void ID::decode_R_type(signed int &s1)
 	s2 = GET_MID_BITS(s1, s0b, s1b);
 	s1 = GET_LS_BITS(s1, s0b);
 
-	if (this->curr_instr->type == SI_INT) {
+	switch (this->curr_instr->type) {
+	case SI_INT:
 		r1 = this->read_guard<signed int>(
 			s1, this->curr_instr->operands.integer.slot_one);
 		r2 = this->read_guard<signed int>(
 			s2, this->curr_instr->operands.integer.slot_two);
 		r3 = OK;
-	} else if (this->curr_instr->type == R_VECT) {
+		break;
+	case R_VECT:
 		r1 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
 			s1, this->curr_instr->operands.vector.slot_one);
 		r2 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
 			s2, this->curr_instr->operands.vector.slot_two);
 		r3 = this->set_vlen();
-	} else {
+		break;
+	case S_VECT:
 		// store the second field in s1, to keep execute+mem consistent
 		r1 = this->read_guard<std::array<signed int, V_R_LIMIT>>(
 			s2, this->curr_instr->operands.s_vector.slot_one);
 		r2 = this->read_guard<signed int>(
 			s1, this->curr_instr->operands.s_vector.slot_two);
 		r3 = this->set_vlen();
+		break;
 	}
 
 	this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED;
@@ -134,6 +138,7 @@ void ID::decode_R_type(signed int &s1)
 			this->curr_instr->operands.vector.slot_three =
 				this->write_guard<std::array<signed int, V_R_LIMIT>>(s3);
 			break;
+		case ROTV:
 		case SRDL:
 			this->curr_instr->operands.s_vector.slot_three =
 				this->write_guard<std::array<signed int, V_R_LIMIT>>(s3);
-- 
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