From 79a68cabb033530871a1dab259149480584b2586 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 11 May 2025 13:08:16 -0400 Subject: Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general --- src/id.cc | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) (limited to 'src/id.cc') diff --git a/src/id.cc b/src/id.cc index 3c974e9..12f509f 100644 --- a/src/id.cc +++ b/src/id.cc @@ -105,33 +105,41 @@ void ID::decode_R_type(signed int &s1) r2 = this->read_guard( s2, this->curr_instr->operands.integer.slot_two); r3 = OK; - } else { + } else if (this->curr_instr->type == R_VECT) { r1 = this->read_guard>( s1, this->curr_instr->operands.vector.slot_one); r2 = this->read_guard>( s2, this->curr_instr->operands.vector.slot_two); r3 = this->set_vlen(); + } else { + // store the second field in s1, to keep execute+mem consistent + r1 = this->read_guard>( + s2, this->curr_instr->operands.s_vector.slot_one); + r2 = this->read_guard( + s1, this->curr_instr->operands.s_vector.slot_two); + r3 = this->set_vlen(); } this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED; - switch (this->curr_instr->mnemonic) { - case CMP: - case CEV: - break; - case ADDV: - case SUBV: - case MULV: - case DIVV: - case SRDL: - case SRDS: - if (this->status == OK) { + if (this->status == OK) { + switch (this->curr_instr->mnemonic) { + case CMP: + case CEV: + break; + case ADDV: + case SUBV: + case MULV: + case DIVV: this->curr_instr->operands.vector.slot_three = this->write_guard>(s3); - } - break; - default: - if (this->status == OK) { + break; + case SRDL: + case SRDS: + this->curr_instr->operands.s_vector.slot_three = + this->write_guard>(s3); + break; + default: this->curr_instr->operands.integer.slot_three = this->write_guard(s3); } @@ -143,7 +151,6 @@ void ID::decode_I_type(signed int &s1) unsigned int s0b, s1b, s2b; signed int s2, s3; Response r1, r2; - Response r3 = OK; s0b = REG_SIZE; s1b = s0b + REG_SIZE; -- cgit v1.2.3