From 26c24ab3c581967015490d1a11ee098bb5ba338a Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 11 May 2025 12:20:33 -0400 Subject: Replaced STOREV with LOADV --- src/instr.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'src/instr.cc') diff --git a/src/instr.cc b/src/instr.cc index ee2d37f..98028fc 100644 --- a/src/instr.cc +++ b/src/instr.cc @@ -23,26 +23,26 @@ namespace instr { const std::unordered_map mnemonic_map = { - {0b0000100, ADD}, {0b0001000, SUB}, {0b0001100, MUL}, - {0b0010000, QUOT}, {0b0010100, REM}, {0b0011000, SFTR}, - {0b0011100, SFTL}, {0b0100000, AND}, {0b0100100, OR}, - {0b0101000, NOT}, {0b0101100, XOR}, {0b0110000, ADDV}, - {0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV}, - {0b1000000, CMP}, {0b1000100, CEV}, {0b000101, LOAD}, - {0b001001, LOADV}, {0b0001101, ADDI}, {0b0010001, SUBI}, - {0b0010101, SFTRI}, {0b0011001, SFTLI}, {0b0011101, ANDI}, - {0b0100001, ORI}, {0b0100101, XORI}, {0b0101001, STORE}, - {0b0101101, STOREV}, {0b0000110, JMP}, {0b0001010, JRL}, - {0b0001110, JAL}, {0b0010010, BEQ}, {0b0010110, BGT}, - {0b0011010, BUF}, {0b0011110, BOF}, {0b0100010, PUSH}, - {0b0100110, POP}, {0b0101010, RET}, + {0b0000100, ADD}, {0b0001000, SUB}, {0b0001100, MUL}, + {0b0010000, QUOT}, {0b0010100, REM}, {0b0011000, SFTR}, + {0b0011100, SFTL}, {0b0100000, AND}, {0b0100100, OR}, + {0b0101000, NOT}, {0b0101100, XOR}, {0b0110000, ADDV}, + {0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV}, + {0b1000000, CMP}, {0b1000100, CEV}, {0b1001000, SRDL}, + {0b1001100, SRDS}, {0b000101, LOAD}, {0b0001001, ADDI}, + {0b0001101, SUBI}, {0b0010001, SFTRI}, {0b0010101, SFTLI}, + {0b0011001, ANDI}, {0b0011101, ORI}, {0b0100001, XORI}, + {0b0100101, STORE}, {0b0000110, JMP}, {0b0001010, JRL}, + {0b0001110, JAL}, {0b0010010, BEQ}, {0b0010110, BGT}, + {0b0011010, BUF}, {0b0011110, BOF}, {0b0100010, PUSH}, + {0b0100110, POP}, {0b0101010, RET}, }; FieldType get_field_types(Mnemonic m) { if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV) { return R_VECT; - } else if (m == STOREV || m == LOADV) { + } else if (m == SRDL || m == SRDS) { return I_VECT; } else { return SI_INT; -- cgit v1.2.3 From 5326509d842c038a2d4f7dcf11fcadf960e437dd Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 11 May 2025 12:31:58 -0400 Subject: Remove I_VECT field types --- inc/instr.h | 1 - src/id.cc | 31 ++----------------------------- src/instr.cc | 5 ++--- src/wb.cc | 10 +++++----- 4 files changed, 9 insertions(+), 38 deletions(-) (limited to 'src/instr.cc') diff --git a/inc/instr.h b/inc/instr.h index 7a6396d..caceb39 100644 --- a/inc/instr.h +++ b/inc/instr.h @@ -64,7 +64,6 @@ enum Mnemonic { enum FieldType { SI_INT, R_VECT, - I_VECT, }; namespace instr diff --git a/src/id.cc b/src/id.cc index 371e3b7..3c974e9 100644 --- a/src/id.cc +++ b/src/id.cc @@ -123,6 +123,8 @@ void ID::decode_R_type(signed int &s1) case SUBV: case MULV: case DIVV: + case SRDL: + case SRDS: if (this->status == OK) { this->curr_instr->operands.vector.slot_three = this->write_guard>(s3); @@ -164,35 +166,6 @@ void ID::decode_I_type(signed int &s1) this->curr_instr->operands.integer.slot_two = s2; this->status = (r1 == OK && r2 == OK) ? OK : STALLED; return; - // case SRDS: - // this->curr_instr->operands.i_vector.slot_two = s3; - // s2 = GET_MID_BITS(s1, s0b, s1b); - // s1 = GET_LS_BITS(s1, s0b); - - // // base address - // r1 = this->read_guard(s1, s1); - // this->curr_instr->operands.i_vector.slot_one = s1; - // // vector value to be stored - // r2 = this->read_guard>( - // s2, this->curr_instr->operands.i_vector.slot_three); - // r3 = this->set_vlen(); - - // this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED; - // return; - // case SRDL: - // this->curr_instr->operands.i_vector.slot_two = s3; - // s2 = GET_LS_BITS(s1, s0b); - // s1 = GET_MID_BITS(s1, s0b, s1b); - // // base address - // r1 = this->read_guard(s1, s1); - // this->curr_instr->operands.i_vector.slot_one = s1; - // r3 = this->set_vlen(); - // if (r1 == OK && r3 == OK) - // // vector destination - // this->curr_instr->operands.i_vector.slot_three = - // this->write_guard>(s2); - // this->status = (r1 == OK && r3 == OK) ? OK : STALLED; - // return; case LOAD: this->curr_instr->operands.integer.slot_three = s3; s2 = GET_LS_BITS(s1, s0b); diff --git a/src/instr.cc b/src/instr.cc index 98028fc..1282147 100644 --- a/src/instr.cc +++ b/src/instr.cc @@ -40,10 +40,9 @@ const std::unordered_map mnemonic_map = { FieldType get_field_types(Mnemonic m) { - if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV) { + if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV || + m == SRDL || m == SRDS) { return R_VECT; - } else if (m == SRDL || m == SRDS) { - return I_VECT; } else { return SI_INT; } diff --git a/src/wb.cc b/src/wb.cc index bfdbc3a..1f396a5 100644 --- a/src/wb.cc +++ b/src/wb.cc @@ -62,11 +62,11 @@ void WB::write_handler() this->store_register>( reg, this->copy_extra_vector_elements()); break; - case I_VECT: - this->store_register>( - reg, this->curr_instr->operands.i_vector.slot_three); - // todo, use copy_extra_vector_elements - break; + // case I_VECT: + // this->store_register>( + // reg, this->curr_instr->operands.i_vector.slot_three); + // // todo, use copy_extra_vector_elements + // break; } } -- cgit v1.2.3 From 79a68cabb033530871a1dab259149480584b2586 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 11 May 2025 13:08:16 -0400 Subject: Add I_VECT field type for SRDL, SRDS, with two vector reg 1 general --- inc/ex.h | 2 +- inc/instr.h | 1 + inc/instrDTO.h | 4 ++-- src/ex.cc | 14 +++++++------- src/id.cc | 41 ++++++++++++++++++++++++----------------- src/instr.cc | 5 +++-- src/wb.cc | 4 ++-- 7 files changed, 40 insertions(+), 31 deletions(-) (limited to 'src/instr.cc') diff --git a/inc/ex.h b/inc/ex.h index 30a6639..19b35d4 100644 --- a/inc/ex.h +++ b/inc/ex.h @@ -96,7 +96,7 @@ class EX : public Stage * @param the mnemonic * @param the vector length register */ - void handle_i_vector_operations(signed int &s1, signed int s2, Mnemonic m); + void handle_s_vector_operations(signed int &s1, signed int s2, Mnemonic m); /** * Wrapper for division functions, which detects HALT instructinos (division * by 0). diff --git a/inc/instr.h b/inc/instr.h index caceb39..a083699 100644 --- a/inc/instr.h +++ b/inc/instr.h @@ -64,6 +64,7 @@ enum Mnemonic { enum FieldType { SI_INT, R_VECT, + S_VECT, }; namespace instr diff --git a/inc/instrDTO.h b/inc/instrDTO.h index ccc6ed9..5d6a4eb 100644 --- a/inc/instrDTO.h +++ b/inc/instrDTO.h @@ -35,7 +35,7 @@ struct V_TYPE { }; struct VI_TYPE { - signed int slot_one; + std::array slot_one; signed int slot_two; std::array slot_three; }; @@ -68,7 +68,7 @@ struct InstrDTO { union { struct U_INT_TYPE integer; struct V_TYPE vector; - struct VI_TYPE i_vector; + struct VI_TYPE s_vector; } operands; }; diff --git a/src/ex.cc b/src/ex.cc index 3328cbe..cd00254 100644 --- a/src/ex.cc +++ b/src/ex.cc @@ -240,7 +240,7 @@ void EX::handle_vector_operations( this->set_condition(UF, underflow); } -void EX::handle_i_vector_operations(signed int &s1, signed int s2, Mnemonic m) +void EX::handle_s_vector_operations(signed int &s1, signed int s2, Mnemonic m) { switch (m) { // case SRDL: @@ -249,7 +249,7 @@ void EX::handle_i_vector_operations(signed int &s1, signed int s2, Mnemonic m) // break; default: - throw std::invalid_argument("handle_i_vector_operations did not " + throw std::invalid_argument("handle_s_vector_operations did not " "receive a SRDL or SRDS operation!"); } } @@ -270,11 +270,11 @@ void EX::advance_helper() handle_vector_operations( this->curr_instr->operands.vector.slot_one, this->curr_instr->operands.vector.slot_two, m, v_len_or_pc); - } else { - handle_i_vector_operations( - this->curr_instr->operands.i_vector.slot_one, - this->curr_instr->operands.i_vector.slot_two, m); - } + }// else { + // handle_s_vector_operations( + // this->curr_instr->operands.s_vector.slot_one, + // this->curr_instr->operands.s_vector.slot_two, m); + // } this->status = OK; } diff --git a/src/id.cc b/src/id.cc index 3c974e9..12f509f 100644 --- a/src/id.cc +++ b/src/id.cc @@ -105,33 +105,41 @@ void ID::decode_R_type(signed int &s1) r2 = this->read_guard( s2, this->curr_instr->operands.integer.slot_two); r3 = OK; - } else { + } else if (this->curr_instr->type == R_VECT) { r1 = this->read_guard>( s1, this->curr_instr->operands.vector.slot_one); r2 = this->read_guard>( s2, this->curr_instr->operands.vector.slot_two); r3 = this->set_vlen(); + } else { + // store the second field in s1, to keep execute+mem consistent + r1 = this->read_guard>( + s2, this->curr_instr->operands.s_vector.slot_one); + r2 = this->read_guard( + s1, this->curr_instr->operands.s_vector.slot_two); + r3 = this->set_vlen(); } this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED; - switch (this->curr_instr->mnemonic) { - case CMP: - case CEV: - break; - case ADDV: - case SUBV: - case MULV: - case DIVV: - case SRDL: - case SRDS: - if (this->status == OK) { + if (this->status == OK) { + switch (this->curr_instr->mnemonic) { + case CMP: + case CEV: + break; + case ADDV: + case SUBV: + case MULV: + case DIVV: this->curr_instr->operands.vector.slot_three = this->write_guard>(s3); - } - break; - default: - if (this->status == OK) { + break; + case SRDL: + case SRDS: + this->curr_instr->operands.s_vector.slot_three = + this->write_guard>(s3); + break; + default: this->curr_instr->operands.integer.slot_three = this->write_guard(s3); } @@ -143,7 +151,6 @@ void ID::decode_I_type(signed int &s1) unsigned int s0b, s1b, s2b; signed int s2, s3; Response r1, r2; - Response r3 = OK; s0b = REG_SIZE; s1b = s0b + REG_SIZE; diff --git a/src/instr.cc b/src/instr.cc index 1282147..271fc99 100644 --- a/src/instr.cc +++ b/src/instr.cc @@ -40,9 +40,10 @@ const std::unordered_map mnemonic_map = { FieldType get_field_types(Mnemonic m) { - if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV || - m == SRDL || m == SRDS) { + if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV) { return R_VECT; + } else if (m == SRDL || m == SRDS) { + return S_VECT; } else { return SI_INT; } diff --git a/src/wb.cc b/src/wb.cc index 1f396a5..fc714ad 100644 --- a/src/wb.cc +++ b/src/wb.cc @@ -62,9 +62,9 @@ void WB::write_handler() this->store_register>( reg, this->copy_extra_vector_elements()); break; - // case I_VECT: + // case S_VECT: // this->store_register>( - // reg, this->curr_instr->operands.i_vector.slot_three); + // reg, this->curr_instr->operands.s_vector.slot_three); // // todo, use copy_extra_vector_elements // break; } -- cgit v1.2.3 From 43588597069587f6846a7d64a1957435bec5429d Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 11 May 2025 22:04:46 -0400 Subject: Add ROTV instruction --- gui/gui.h | 12 ++++++------ inc/ex.h | 1 - inc/instr.h | 1 + src/ex.cc | 8 +++++++- src/id.cc | 11 ++++++++--- src/instr.cc | 16 ++++++++-------- 6 files changed, 30 insertions(+), 19 deletions(-) (limited to 'src/instr.cc') diff --git a/gui/gui.h b/gui/gui.h index d0b8e47..a1d97ad 100644 --- a/gui/gui.h +++ b/gui/gui.h @@ -165,12 +165,12 @@ class GUI : public QMainWindow {Mnemonic::ANDI, "ANDI"}, {Mnemonic::ORI, "ORI"}, {Mnemonic::XORI, "XORI"}, {Mnemonic::STORE, "STORE"}, {Mnemonic::SRDL, "SRDL"}, {Mnemonic::SRDS, "SRDS"}, - {Mnemonic::JMP, "JMP"}, {Mnemonic::JRL, "JRL"}, - {Mnemonic::JAL, "JAL"}, {Mnemonic::BEQ, "BEQ"}, - {Mnemonic::BGT, "BGT"}, {Mnemonic::BUF, "BUF"}, - {Mnemonic::BOF, "BOF"}, {Mnemonic::PUSH, "PUSH"}, - {Mnemonic::POP, "POP"}, {Mnemonic::NOP, "NOP"}, - {Mnemonic::RET, "RET"}, + {Mnemonic::ROTV, "ROTV"}, {Mnemonic::JMP, "JMP"}, + {Mnemonic::JRL, "JRL"}, {Mnemonic::JAL, "JAL"}, + {Mnemonic::BEQ, "BEQ"}, {Mnemonic::BGT, "BGT"}, + {Mnemonic::BUF, "BUF"}, {Mnemonic::BOF, "BOF"}, + {Mnemonic::PUSH, "PUSH"}, {Mnemonic::POP, "POP"}, + {Mnemonic::NOP, "NOP"}, {Mnemonic::RET, "RET"}, }; QString mnemonicToString(Mnemonic mnemonic) { diff --git a/inc/ex.h b/inc/ex.h index 41195a1..64eecb7 100644 --- a/inc/ex.h +++ b/inc/ex.h @@ -89,7 +89,6 @@ class EX : public Stage /** * Handles operations involving a vector result and a scalar. - * Currently, this is SRDL and SRDS * @param slot 1, and later, the result of the mnemonic operation. * @param slot 2 * @param the mnemonic diff --git a/inc/instr.h b/inc/instr.h index a083699..5a8ff4a 100644 --- a/inc/instr.h +++ b/inc/instr.h @@ -39,6 +39,7 @@ enum Mnemonic { CEV, SRDL, SRDS, + ROTV, LOAD, ADDI, SUBI, diff --git a/src/ex.cc b/src/ex.cc index 22cd092..f36ea4b 100644 --- a/src/ex.cc +++ b/src/ex.cc @@ -249,6 +249,13 @@ void EX::handle_s_vector_operations( unsigned int i, inc1, inc2; switch (m) { + case ROTV: + s2 = s2 % v_len; + if (s2 < 0) + s2 += v_len; + + std::rotate(s1.begin(), s1.begin() + s2, s1.begin() + v_len); + break; case SRDL: case SRDS: inc1 = s1[0]; @@ -286,7 +293,6 @@ void EX::advance_helper() handle_s_vector_operations( this->curr_instr->operands.s_vector.slot_one, this->curr_instr->operands.s_vector.slot_two, m, v_len_or_pc); - printArray(this->curr_instr->operands.s_vector.slot_three); } this->status = OK; diff --git a/src/id.cc b/src/id.cc index 9547486..58bde6b 100644 --- a/src/id.cc +++ b/src/id.cc @@ -99,25 +99,29 @@ void ID::decode_R_type(signed int &s1) s2 = GET_MID_BITS(s1, s0b, s1b); s1 = GET_LS_BITS(s1, s0b); - if (this->curr_instr->type == SI_INT) { + switch (this->curr_instr->type) { + case SI_INT: r1 = this->read_guard( s1, this->curr_instr->operands.integer.slot_one); r2 = this->read_guard( s2, this->curr_instr->operands.integer.slot_two); r3 = OK; - } else if (this->curr_instr->type == R_VECT) { + break; + case R_VECT: r1 = this->read_guard>( s1, this->curr_instr->operands.vector.slot_one); r2 = this->read_guard>( s2, this->curr_instr->operands.vector.slot_two); r3 = this->set_vlen(); - } else { + break; + case S_VECT: // store the second field in s1, to keep execute+mem consistent r1 = this->read_guard>( s2, this->curr_instr->operands.s_vector.slot_one); r2 = this->read_guard( s1, this->curr_instr->operands.s_vector.slot_two); r3 = this->set_vlen(); + break; } this->status = (r1 == OK && r2 == OK && r3 == OK) ? OK : STALLED; @@ -134,6 +138,7 @@ void ID::decode_R_type(signed int &s1) this->curr_instr->operands.vector.slot_three = this->write_guard>(s3); break; + case ROTV: case SRDL: this->curr_instr->operands.s_vector.slot_three = this->write_guard>(s3); diff --git a/src/instr.cc b/src/instr.cc index 271fc99..a638a38 100644 --- a/src/instr.cc +++ b/src/instr.cc @@ -29,20 +29,20 @@ const std::unordered_map mnemonic_map = { {0b0101000, NOT}, {0b0101100, XOR}, {0b0110000, ADDV}, {0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV}, {0b1000000, CMP}, {0b1000100, CEV}, {0b1001000, SRDL}, - {0b1001100, SRDS}, {0b000101, LOAD}, {0b0001001, ADDI}, - {0b0001101, SUBI}, {0b0010001, SFTRI}, {0b0010101, SFTLI}, - {0b0011001, ANDI}, {0b0011101, ORI}, {0b0100001, XORI}, - {0b0100101, STORE}, {0b0000110, JMP}, {0b0001010, JRL}, - {0b0001110, JAL}, {0b0010010, BEQ}, {0b0010110, BGT}, - {0b0011010, BUF}, {0b0011110, BOF}, {0b0100010, PUSH}, - {0b0100110, POP}, {0b0101010, RET}, + {0b1001100, SRDS}, {0b1010000, ROTV}, {0b000101, LOAD}, + {0b0001001, ADDI}, {0b0001101, SUBI}, {0b0010001, SFTRI}, + {0b0010101, SFTLI}, {0b0011001, ANDI}, {0b0011101, ORI}, + {0b0100001, XORI}, {0b0100101, STORE}, {0b0000110, JMP}, + {0b0001010, JRL}, {0b0001110, JAL}, {0b0010010, BEQ}, + {0b0010110, BGT}, {0b0011010, BUF}, {0b0011110, BOF}, + {0b0100010, PUSH}, {0b0100110, POP}, {0b0101010, RET}, }; FieldType get_field_types(Mnemonic m) { if (m == ADDV || m == SUBV || m == MULV || m == DIVV || m == CEV) { return R_VECT; - } else if (m == SRDL || m == SRDS) { + } else if (m == SRDL || m == SRDS || m == ROTV) { return S_VECT; } else { return SI_INT; -- cgit v1.2.3