From b81c86b438123457be86af2e7c24375856afa742 Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 26 Mar 2025 12:21:52 -0400 Subject: Add fetch stage implementation, tests, program loading, DTO object --- src/sim/controller.cc | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) (limited to 'src/sim/controller.cc') diff --git a/src/sim/controller.cc b/src/sim/controller.cc index 93fd0e0..2813905 100644 --- a/src/sim/controller.cc +++ b/src/sim/controller.cc @@ -1,34 +1,23 @@ #include "controller.h" -#include "ex.h" -#include "id.h" -#include "if.h" -#include "mm.h" #include "response.h" #include "storage.h" -#include "wb.h" -Controller::Controller(Storage *storage, bool is_pipelined) - : Stage(nullptr) +Controller::Controller(Stage *stage, Storage *storage, bool is_pipelined) + : Stage(stage) { this->clock_cycle = 0; this->storage = storage; this->is_pipelined = is_pipelined; this->pc = 0x0; this->gprs = {0}; - - IF *f = new IF(nullptr); - ID *d = new ID(f); - EX *e = new EX(d); - MM *m = new MM(e); - WB *w = new WB(m); - this->next = w; } void Controller::run_for(int number) { + InstrDTO instr; int i; for (i = 0; i < number; ++i) { - this->advance(); + this->advance(instr); } } @@ -38,9 +27,11 @@ std::array Controller::get_gprs() { return this->gprs; } int Controller::get_pc() { return this->pc; } -Response Controller::advance() +Response Controller::advance(InstrDTO &i) { - this->next->advance(); + Response r; + + r = this->next->advance(i); ++this->clock_cycle; - return OK; + return r; } -- cgit v1.2.3 From 8d37d15ebd1221e3b1698abb3b051d9d0c044c93 Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 26 Mar 2025 22:01:54 -0400 Subject: Fix timing issues in fetch tests --- src/sim/controller.cc | 2 +- tests/controller.cc | 2 +- tests/if.cc | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/sim/controller.cc') diff --git a/src/sim/controller.cc b/src/sim/controller.cc index 2813905..6d46dc4 100644 --- a/src/sim/controller.cc +++ b/src/sim/controller.cc @@ -5,7 +5,7 @@ Controller::Controller(Stage *stage, Storage *storage, bool is_pipelined) : Stage(stage) { - this->clock_cycle = 0; + this->clock_cycle = 1; this->storage = storage; this->is_pipelined = is_pipelined; this->pc = 0x0; diff --git a/tests/controller.cc b/tests/controller.cc index a2f8e7d..e3b9f3c 100644 --- a/tests/controller.cc +++ b/tests/controller.cc @@ -43,7 +43,7 @@ TEST_CASE_METHOD( gprs = this->ct->get_gprs(); - CHECK(this->ct->get_clock_cycle() == 0); + CHECK(this->ct->get_clock_cycle() == 1); CHECK(std::all_of( gprs.begin(), gprs.end(), [](int value) { return value == 0; })); // change me later diff --git a/tests/if.cc b/tests/if.cc index 86458d2..5c1b645 100644 --- a/tests/if.cc +++ b/tests/if.cc @@ -74,7 +74,7 @@ TEST_CASE_METHOD(IFPipeFixture, "fetch returns single instuction", "[if_pipe]") InstrDTO instr; int expected_cycles; - expected_cycles = this->m_delay + this->c_delay + 1; + expected_cycles = this->m_delay + this->c_delay + 2; this->fetch_through(instr); CHECK(instr.get_if_cycle() == expected_cycles); @@ -86,7 +86,7 @@ TEST_CASE_METHOD(IFPipeFixture, "fetch returns two instuctions", "[if_pipe]") InstrDTO instr; int expected_cycles; - expected_cycles = this->m_delay + this->c_delay + 1; + expected_cycles = this->m_delay + this->c_delay + 2; this->fetch_through(instr); CHECK(instr.get_if_cycle() == expected_cycles); -- cgit v1.2.3