From 8d37d15ebd1221e3b1698abb3b051d9d0c044c93 Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 26 Mar 2025 22:01:54 -0400 Subject: Fix timing issues in fetch tests --- src/sim/controller.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/sim/controller.cc') diff --git a/src/sim/controller.cc b/src/sim/controller.cc index 2813905..6d46dc4 100644 --- a/src/sim/controller.cc +++ b/src/sim/controller.cc @@ -5,7 +5,7 @@ Controller::Controller(Stage *stage, Storage *storage, bool is_pipelined) : Stage(stage) { - this->clock_cycle = 0; + this->clock_cycle = 1; this->storage = storage; this->is_pipelined = is_pipelined; this->pc = 0x0; -- cgit v1.2.3