From 598da346f59503442ba0b4badfd9ac8b58af4a89 Mon Sep 17 00:00:00 2001
From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>
Date: Mon, 31 Mar 2025 13:45:56 -0400
Subject: MEM WB stage

---
 src/sim/ex.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/sim/ex.cc')

diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index 95cce8d..f22adc0 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -282,28 +282,28 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			BEQ,
 			{
-				s1 = this->pc + s2;
+				(this->get_condition(EQ)) ? s1 = this->pc + s2 : s1 = this->pc;
 				(void)s3;
 			}),
 
 		INIT_INSTRUCTION(
 			BGT,
 			{
-				s1 = this->pc + s2;
+				(this->get_condition(GT)) ? s1 = this->pc + s2 : s1 = this->pc;
 				(void)s3;
 			}),
 
 		INIT_INSTRUCTION(
 			BUF,
 			{
-				s1 = this->pc + s2;
+				(this->get_condition(UF)) ? s1 = this->pc + s2 : s1 = this->pc;
 				(void)s3;
 			}),
 
 		INIT_INSTRUCTION(
 			BOF,
 			{
-				s1 = this->pc + s2;
+				(this->get_condition(OF)) ? s1 = this->pc + s2 : s1 = this->pc;
 				(void)s3;
 			}),
 
-- 
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