From 6557e7e623140871968776429d241570002a65f5 Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Sun, 30 Mar 2025 12:33:25 -0400
Subject: Setting condition code register, overflow guard

---
 src/sim/stage.cc | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/sim/stage.cc')

diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 62a7fd6..d8c882a 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -21,6 +21,18 @@ Storage *Stage::storage;
 bool Stage::is_pipelined;
 int Stage::clock_cycle;
 
+void Stage::set_condition(CC c, bool v)
+{
+	if (v)
+		this->gprs[3] = this->gprs[3] & 1 << c;
+	else
+		this->gprs[3] = this->gprs[3] & ~(1 << c);
+}
+
+bool Stage::get_condition(CC c) {
+	return (this->gprs[3] >> c) & 1;
+}
+
 signed int Stage::dereference_register(signed int v)
 {
 	signed int r;
-- 
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