From 598da346f59503442ba0b4badfd9ac8b58af4a89 Mon Sep 17 00:00:00 2001
From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>
Date: Mon, 31 Mar 2025 13:45:56 -0400
Subject: MEM WB stage

---
 src/sim/wb.cc | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

(limited to 'src/sim/wb.cc')

diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 9337aa0..480af05 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -6,4 +6,32 @@
 
 WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }
 
-void WB::advance_helper() {}
+void WB::advance_helper() {
+    if(this -> curr_instr) {
+        if(this->curr_instr->get_type() == R || this->curr_instr->get_type() == I){ 
+            if(this->checked_out.size() > 0) {
+                signed int reg = this->checked_out.front();
+                this->checked_out.pop_front();
+                if(reg >= GPR_NUM){
+                    // TODO: handle vector instructions
+                } else {
+                    this->gprs[reg] = this->curr_instr->get_s1();
+                }
+            }
+        } else if (this->curr_instr->get_type() == J) {
+            // TODO:handle push pop
+            // branch taken
+            if(this->pc != this->curr_instr->get_s1()) {
+                if(this->curr_instr->get_mnemonic() == JAL){
+                    // set link register to next instruction
+                    this->gprs[1] = this->pc + 1;
+                }
+                this->pc = this->curr_instr->get_s1();  
+                //clear pending registers and squash pipeline
+                this->checked_out = {};
+                this->next->squash();
+            }
+        }
+    }
+    this->status = OK;
+}
-- 
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