From 598da346f59503442ba0b4badfd9ac8b58af4a89 Mon Sep 17 00:00:00 2001
From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>
Date: Mon, 31 Mar 2025 13:45:56 -0400
Subject: MEM WB stage

---
 src/sim/wb.cc | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

(limited to 'src/sim/wb.cc')

diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 9337aa0..480af05 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -6,4 +6,32 @@
 
 WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }
 
-void WB::advance_helper() {}
+void WB::advance_helper() {
+    if(this -> curr_instr) {
+        if(this->curr_instr->get_type() == R || this->curr_instr->get_type() == I){ 
+            if(this->checked_out.size() > 0) {
+                signed int reg = this->checked_out.front();
+                this->checked_out.pop_front();
+                if(reg >= GPR_NUM){
+                    // TODO: handle vector instructions
+                } else {
+                    this->gprs[reg] = this->curr_instr->get_s1();
+                }
+            }
+        } else if (this->curr_instr->get_type() == J) {
+            // TODO:handle push pop
+            // branch taken
+            if(this->pc != this->curr_instr->get_s1()) {
+                if(this->curr_instr->get_mnemonic() == JAL){
+                    // set link register to next instruction
+                    this->gprs[1] = this->pc + 1;
+                }
+                this->pc = this->curr_instr->get_s1();  
+                //clear pending registers and squash pipeline
+                this->checked_out = {};
+                this->next->squash();
+            }
+        }
+    }
+    this->status = OK;
+}
-- 
cgit v1.2.3


From 574212dafcf1c4bdb7d5e6aaa577b74345988d67 Mon Sep 17 00:00:00 2001
From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com>
Date: Mon, 31 Mar 2025 20:51:20 -0400
Subject: CR Comments

---
 src/sim/id.cc       | 2 +-
 src/sim/instrDTO.cc | 2 +-
 src/sim/stage.cc    | 2 +-
 src/sim/wb.cc       | 4 +++-
 4 files changed, 6 insertions(+), 4 deletions(-)

(limited to 'src/sim/wb.cc')

diff --git a/src/sim/id.cc b/src/sim/id.cc
index deb69fb..0b75b64 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -50,7 +50,7 @@ void ID::advance_helper()
 
 	// it may be good to ensure we are not doing
 	// work that has already been done
-	if (this->curr_instr) {
+	if (this->curr_instr && this->curr_instr->get_mnemonic() == NONE) {
 		s1 = curr_instr->get_instr_bits();
 		get_instr_fields(s1, s2, s3, m ,t);
 		if (this->status == OK) {
diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc
index 28364b7..b33c26b 100644
--- a/src/sim/instrDTO.cc
+++ b/src/sim/instrDTO.cc
@@ -7,7 +7,7 @@ InstrDTO::InstrDTO()
 	this->s1 = 0;
 	this->s2 = 0;
 	this->s3 = 0;
-	this->mnemonic = NOP;
+	this->mnemonic = NONE;
 	this->type = INV;
 }
 
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 26b6ee6..be69d77 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -80,7 +80,7 @@ bool Stage::is_checked_out(signed int r)
 }
 
 void Stage::squash(){
-	this->curr_instr = nullptr;
+	this->curr_instr->set_mnemonic(NOP);
 	this->status = OK;
 	if(this->next){
 		this->next->squash();
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 480af05..ac47f25 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -15,7 +15,9 @@ void WB::advance_helper() {
                 if(reg >= GPR_NUM){
                     // TODO: handle vector instructions
                 } else {
-                    this->gprs[reg] = this->curr_instr->get_s1();
+                    if(this->curr_instr->get_mnemonic() != STORE && this->curr_instr->get_mnemonic() != STOREV){
+                        this->gprs[reg] = this->curr_instr->get_s1();
+                    }
                 }
             }
         } else if (this->curr_instr->get_type() == J) {
-- 
cgit v1.2.3