From 7b3abbd51c91b51725a12d17fad6ecbfcdb19975 Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Fri, 28 Mar 2025 19:55:04 -0400
Subject: Move get_instr_fields, add all instruction mnemonics

---
 src/sim/id.cc    | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 src/sim/instr.cc | 27 ++++++++++++++++++++------
 2 files changed, 78 insertions(+), 7 deletions(-)

(limited to 'src/sim')

diff --git a/src/sim/id.cc b/src/sim/id.cc
index 87dce0c..65acef5 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -1,9 +1,65 @@
 #include "id.h"
 #include "accessor.h"
 #include "instrDTO.h"
+#include "logger.h"
 #include "response.h"
 #include "stage.h"
+#include "utils.h"
+
+static Logger *global_log = Logger::getInstance();
 
 ID::ID(Stage *stage) : Stage(stage) { this->id = DCDE; }
 
-Response ID::advance(InstrDTO &i) { return OK; }
+Response ID::advance(InstrDTO &i) { Response r; }
+
+void ID::get_instr_fields(
+	signed int &s1,
+	signed int &s2,
+	signed int &s3,
+	unsigned int &type,
+	unsigned int &opcode)
+{
+	// unsigned int &opcode;
+	int opcode_bits;
+
+	type = GET_LS_BITS(s1, TYPE_SIZE);
+	opcode_bits = (type == 0b0) ? R_OPCODE_SIZE : OPCODE_SIZE;
+
+	switch (type) {
+	case 0:
+		// R-TYPE
+		opcode += GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits);
+		s3 = GET_MID_BITS(
+			s1, TYPE_SIZE + opcode_bits + (REG_SIZE * 2),
+			TYPE_SIZE + opcode_bits + (REG_SIZE * 3));
+		s2 = GET_MID_BITS(
+			s1, TYPE_SIZE + opcode_bits + REG_SIZE,
+			TYPE_SIZE + opcode_bits + (REG_SIZE * 2));
+		s1 = GET_MID_BITS(
+			s1, TYPE_SIZE + opcode_bits,
+			TYPE_SIZE + opcode_bits + REG_SIZE);
+		break;
+	case 1:
+		// I-TYPE
+		opcode = GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits);
+		s3 = GET_MID_BITS(
+			s1, TYPE_SIZE + opcode_bits + (REG_SIZE * 2), WORD_SPEC);
+		s2 = GET_MID_BITS(
+			s1, TYPE_SIZE + opcode_bits + REG_SIZE,
+			TYPE_SIZE + opcode_bits + (REG_SIZE * 2));
+		s1 = GET_MID_BITS(
+			s1, TYPE_SIZE + opcode_bits, TYPE_SIZE + opcode_bits + REG_SIZE);
+		break;
+	case 2:
+		// J-TYPE
+		opcode = GET_MID_BITS(s1, TYPE_SIZE, TYPE_SIZE + opcode_bits);
+		s2 = GET_MID_BITS(s1, TYPE_SIZE + OPCODE_SIZE + REG_SIZE, WORD_SPEC);
+		s1 = GET_MID_BITS(
+			s1, TYPE_SIZE + OPCODE_SIZE, TYPE_SIZE + OPCODE_SIZE + REG_SIZE);
+		break;
+	default:
+		global_log->log(
+			DEBUG,
+			string_format("%s returning invalid type: %d", __FUNCTION__, type));
+	}
+}
diff --git a/src/sim/instr.cc b/src/sim/instr.cc
index 608b871..50aa71d 100644
--- a/src/sim/instr.cc
+++ b/src/sim/instr.cc
@@ -3,16 +3,16 @@
 #include <map>
 
 // clang-format off
-#define INIT_INSTRUCTION(type, opcode, body) \
-	{type, {{opcode, [](signed int &s1, signed int &s2, signed int &s3) { \
+#define INIT_INSTRUCTION(mnemonic, body) \
+	{mnemonic, [](signed int &s1, signed int &s2, signed int &s3) { \
 		body; \
-	}}}}
+	}}
 // clang-format on
 
 namespace instr
 {
 // clang-format off
-const std::map<int,	std::map<int, std::function<void(signed int &s1, signed int &s2, signed int &s3)>>>
+const std::map<Mnemonic, std::function<void(signed int &s1, signed int &s2, signed int &s3)>>
 	// clang-format on
 	instr_map = {
 
@@ -20,11 +20,26 @@ const std::map<int,	std::map<int, std::function<void(signed int &s1, signed int
 		// TODO these need to be WRAPPED with a function that sets overflow.
 		// future note to self, if these are more than 2 lines each, you're
 		// doing it wrong
-		INIT_INSTRUCTION(0b00, 0b00001, s3 = s1 + s2),
-		INIT_INSTRUCTION(0b00, 0b00010, s3 = s1 - s2),
+		INIT_INSTRUCTION(ADD, s3 = s1 + s2),
+		INIT_INSTRUCTION(SUB, s3 = s1 - s2),
 
 		/* I type instructions */
 
 		/* J type instructions */
 };
+
+const std::map<unsigned int, Mnemonic> mnemonic_map = {
+	{0b0000100, ADD},  {0b0001000, SUB},  {0b0001100, MUL},	 {0b0010000, QUOT},
+	{0b0010100, REM},  {0b0011000, SFTR}, {0b0011100, SFTL}, {0b0100000, AND},
+	{0b0100100, OR},   {0b0101000, NOT},  {0b0101100, XOR},	 {0b0110000, ADDV},
+	{0b0110100, SUBV}, {0b0111000, MULV}, {0b0111100, DIVV}, {0b1000000, CMP},
+	{0b1000100, CEV},  {0b000101, LOAD},  {0b001001, LOADV}, {0b001101, ADDI},
+	{0b010001, SUBI},  {0b010101, SFTRI}, {0b011101, SFTLI}, {0b100001, ANDI},
+	{0b100101, ORI},   {0b101001, XORI},  {0b101101, STORE}, {0b110001, STOREV},
+	{0b000101, CEV},   {0b000101, LOAD},  {0b001001, LOADV}, {0b001001, LOADV},
+	{0b000110, JMP},   {0b001010, JRL},	  {0b001110, JAL},	 {0b010010, BEQ},
+	{0b010110, BGT},   {0b011010, BUF},	  {0b011110, BOF},	 {0b100010, PUSH},
+	{0b100110, POP},
+
+};
 } // namespace instr
-- 
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