From 6bfae0ef7c7583cfd8a9771332db74ee6eb77a68 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 18:28:08 -0400 Subject: Move do_write to dram.h, is_blocked flag --- src/storage/dram.cc | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/storage/dram.cc') diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 0db4c35..e3f3c9a 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -15,6 +15,14 @@ Dram::Dram(int lines, int delay) Dram::~Dram() { delete this->data; } +void Dram::do_write(signed data, int address) +{ + int line = address / LINE_SIZE; + int word = address % LINE_SIZE; + + this->data->at(line).at(word) = data; +} + Response Dram::write(Accessor accessor, signed int data, int address) { Response r = WAIT; -- cgit v1.2.3 From 968df039670dd3996487add3569180c415ec3a4b Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 20:15:45 -0400 Subject: Untested implementation for loading absent data into cache --- inc/cache.h | 12 ++++++------ inc/storage.h | 6 +++--- src/storage/cache.cc | 38 ++++++++++++++++++++++++++++++++------ src/storage/dram.cc | 11 +++++++---- src/storage/storage.cc | 2 +- 5 files changed, 49 insertions(+), 20 deletions(-) (limited to 'src/storage/dram.cc') diff --git a/inc/cache.h b/inc/cache.h index a317f5d..c8c9736 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -30,17 +30,17 @@ class Cache : public Storage /** * Fetches `address` from a lower level of storage if it is not already * present. If it is not, temporarily sets the is_blocked attribute of this - * cache level to true. + * cache level to true, and the victim line is chosen/written back. * @param the address that must be present in cache. */ void fetch_resource(int address); /** - * An array of paired bits. - * If the least significant bit of an element is set, the corresponding - * element in `data` is invalid. If the most significant bit of an element - * is set, the corresponding element in `data` is dirty. + * An array of metadata about elements in `data`. + * If the first value of an element is negative, the corresponding + * element in `data` is invalid. If the most second value of an element + * is nonzero, the corresponding element in `data` is dirty. */ - std::array, L1_CACHE_SIZE> stat; + std::array, L1_CACHE_SIZE> meta; }; #endif /* CACHE_H_INCLUDED */ diff --git a/inc/storage.h b/inc/storage.h index 9707041..793b982 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -73,10 +73,10 @@ class Storage */ int wait_time; /** - * A flag indicating whether this level of storage is currently blocked by a - * lower level. + * A flag indicating whether this level of storage is currently waiting for + * a lower level. */ - int is_blocked; + int is_waiting; }; #endif /* STORAGE_H_INCLUDED */ diff --git a/src/storage/cache.cc b/src/storage/cache.cc index e0eaf58..ec14ce6 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -1,6 +1,7 @@ #include "cache.h" #include "definitions.h" #include "response.h" +#include "utils.h" #include Cache::Cache(int lines, Storage *lower, int delay) @@ -9,8 +10,7 @@ Cache::Cache(int lines, Storage *lower, int delay) this->data->resize(L1_CACHE_SIZE); this->lower = lower; this->delay = delay; - for (int i = 0; i < L1_CACHE_SIZE; ++i) - this->stat[i] = 0b01; + this->meta.fill({-1}); } Cache::~Cache() { delete this->data; } @@ -25,8 +25,9 @@ Response Cache::write(Accessor accessor, signed int data, int address) if (this->requester == accessor) { fetch_resource(address); - if (this->wait_time == 0) { - // this->do_write(data, address); + if (this->is_waiting == true) + r = BLOCKED; + else if (this->wait_time == 0) { r = OK; } } @@ -34,8 +35,33 @@ Response Cache::write(Accessor accessor, signed int data, int address) return r; } -Response Cache::read(Accessor accessor, int address, std::array& data) { return WAIT; } +Response Cache::read( + Accessor accessor, int address, std::array &data) +{ + return WAIT; +} + +void Cache::fetch_resource(int expected) +{ + Response r = OK; + int etag, index, atag; + std::array actual; + std::array meta; -void Cache::fetch_resource(int address) { + get_bit_fields(expected, &etag, &index, nullptr); + meta = this->meta.at(index); + + if (atag != etag) { + // address not in cache + if (this->meta[index][0]) { + // occupant is dirty + // TODO + r = WAIT; + } else { + actual = this->data->at(index); + r = this->lower->read(L1CACHE, expected, actual); + } + } + this->is_waiting = (r == OK) ? false : true; } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index e3f3c9a..23dedc0 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -46,12 +46,15 @@ Response Dram::write(Accessor accessor, signed int data, int address) return r; } -void Dram::do_read(std::array& data_line, int address){ +void Dram::do_read(std::array &data_line, int address) +{ int line = address / LINE_SIZE; data_line = this->data->at(line); } -Response Dram::read(Accessor accessor, int address, std::array& data) { +Response Dram::read( + Accessor accessor, int address, std::array &data) +{ Response r = WAIT; if (this->requester == IDLE) this->requester = accessor; @@ -61,5 +64,5 @@ Response Dram::read(Accessor accessor, int address, std::arraywait_time == 0) { this->requester = IDLE; this->wait_time = delay; - } else if (this->requester != IDLE && !this->is_blocked) { + } else if (this->requester != IDLE && !this->is_waiting) { --this->wait_time; } } -- cgit v1.2.3 From 0b8679a7f74f22bfb1132e10e450df636e9bb6b2 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 20:55:45 -0400 Subject: initialize wait_time in dram to resolve undefined behavior --- src/storage/dram.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/storage/dram.cc') diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 23dedc0..9dab4ed 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -8,9 +8,10 @@ Dram::Dram(int lines, int delay) this->data = new std::vector>; this->data->resize(lines); this->delay = delay; - this->wait_time = this->delay; + this->is_waiting = false; this->lower = nullptr; this->requester = IDLE; + this->wait_time = this->delay; } Dram::~Dram() { delete this->data; } -- cgit v1.2.3 From 7506edbc6b8c761c3e810f09fd88c1dc7ab3e717 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 23:49:29 -0400 Subject: Properly set cache metadata when a value is loaded --- src/storage/cache.cc | 15 +++-- src/storage/dram.cc | 3 + tests/cache.cc | 169 ++++++++++++++++++++++++++++++++++++++------------- 3 files changed, 139 insertions(+), 48 deletions(-) (limited to 'src/storage/dram.cc') diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 52f13b9..2031367 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -34,6 +34,7 @@ Response Cache::write(Accessor accessor, signed int data, int address) int tag, index, offset; get_bit_fields(address, &tag, &index, &offset); this->data->at(index).at(offset) = data; + this->meta[index].at(1) = 1; r = OK; } } @@ -52,22 +53,24 @@ void Cache::fetch_resource(int expected) Response r = OK; int tag, index, offset; std::array actual; - std::array meta; + std::array *meta; get_bit_fields(expected, &tag, &index, &offset); - meta = this->meta.at(index); + meta = &this->meta.at(index); - if (this->meta[index][0] != tag) { + if (meta->at(0) != tag) { // address not in cache - if (this->meta[index][1] >= 0) { + if (meta->at(1) >= 0) { // occupant is dirty // TODO r = WAIT; } else { actual = this->data->at(index); r = this->lower->read(L1CACHE, expected, actual); - // clear dirty bit and set tag? - + if (r == OK) { + meta->at(0) = tag; + meta->at(1) = -1; + } } } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 9dab4ed..441f10b 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -57,13 +57,16 @@ Response Dram::read( Accessor accessor, int address, std::array &data) { Response r = WAIT; + if (this->requester == IDLE) this->requester = accessor; + if (this->requester == accessor) { if (this->wait_time == 0) { this->do_read(data, address); r = OK; } } + return r; } diff --git a/tests/cache.cc b/tests/cache.cc index 9e6521a..64819b6 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -42,45 +42,130 @@ TEST_CASE("no delay stores instantly", "[cache]") delete c; } -// TEST_CASE("cache takes \"forever\"", "[cache]") -// { -// int delay = 0; -// Dram *d = new Dram(MEM_SIZE, delay); -// Cache *c = new Cache(d, delay + 2); -// std::array expected = {0, 0, 0, 0}; -// std::array actual = d->view(0, 1)[0]; -// CHECK(expected == actual); - -// signed int w = 0x11223344; - -// int i; -// Response r; -// for (i = 0; i < delay + 2; ++i) { -// r = c->write(MEM, w, 0x0000000000000); -// CHECK(r == WAIT); - -// // keep dram busy -// r = d->write(MEM, w, 0x0000000000101); -// CHECK(r == OK); - -// actual = c->view(0, 1)[0]; -// REQUIRE(expected == actual); -// c->resolve(); -// d->resolve(); -// } - -// r = c->write(MEM, w, 0x0000000000000); -// CHECK(r == OK); -// d->resolve(); - -// actual = d->view(0, 1)[0]; -// // we do NOT write back now! -// REQUIRE(expected == actual); - -// expected.at(1) = w; -// actual = c->view(0, 1)[0]; -// REQUIRE(expected == actual); - -// delete d; -// delete c; -// } +TEST_CASE("cache takes \"forever\"", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay); + Cache *c = new Cache(d, delay + 2); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == WAIT); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +TEST_CASE("dram takes \"forever\"", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay + 2); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == BLOCKED); // BLOCKED + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +TEST_CASE("dram and cache take \"forever\"", "[cache]") +{ + int delay = 2; + Dram *d = new Dram(MEM_SIZE, delay + 2); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == BLOCKED); // BLOCKED + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + for (i = 0; i < delay; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == WAIT); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + c->resolve(); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} -- cgit v1.2.3