From 20fe698a4074df4abe02f14a1a14481770e90abc Mon Sep 17 00:00:00 2001 From: bd Date: Thu, 6 Mar 2025 00:03:00 -0500 Subject: Storage.view method, some initial tests --- src/storage/storage.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 src/storage/storage.cc (limited to 'src/storage/storage.cc') diff --git a/src/storage/storage.cc b/src/storage/storage.cc new file mode 100644 index 0000000..49d8e7e --- /dev/null +++ b/src/storage/storage.cc @@ -0,0 +1,12 @@ +#include "storage.h" +#include + +std::vector> Storage::view(int base, int lines) +{ + base = (base / 4) * 4; + std::vector> ret(lines + 1); + std::copy( + this->data->begin() + base, this->data->begin() + base + lines, + ret.begin()); + return ret; +} -- cgit v1.2.3 From 3322aa0845f7fe9cc98aa4e429bd5ecf72a5c27e Mon Sep 17 00:00:00 2001 From: bd Date: Thu, 6 Mar 2025 00:34:35 -0500 Subject: dram write (no delay, no accessor tracking --- inc/cache.h | 2 +- inc/definitions.h | 10 ++++++++++ inc/dram.h | 2 +- inc/storage.h | 5 +++-- src/storage/cache.cc | 3 ++- src/storage/dram.cc | 12 ++++++++++-- src/storage/storage.cc | 8 +++++--- tests/cache.cc | 11 ++++++----- tests/dram.cc | 30 ++++++++++++++++++++++++++---- 9 files changed, 64 insertions(+), 19 deletions(-) create mode 100644 inc/definitions.h (limited to 'src/storage/storage.cc') diff --git a/inc/cache.h b/inc/cache.h index 4d143aa..312f3d1 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -8,7 +8,7 @@ class Cache : public Storage /** * Constructor. * @param The number of `lines` contained in memory. The total number of - * words is this number multiplied by 4. + * words is this number multiplied by LINE_SIZE. * @param The next lowest level in storage. Methods from this object are * called in case of a cache miss. * @param The number of clock cycles each access takes. diff --git a/inc/definitions.h b/inc/definitions.h new file mode 100644 index 0000000..1593162 --- /dev/null +++ b/inc/definitions.h @@ -0,0 +1,10 @@ +#ifndef DEFINITIONS_H +#define DEFINITIONS_H + +/** + * Defines common macros. + */ + +#define LINE_SIZE 4 + +#endif /* DEFINITIONS_H_INCLUDED */ diff --git a/inc/dram.h b/inc/dram.h index 6d33534..c1e86b9 100644 --- a/inc/dram.h +++ b/inc/dram.h @@ -8,7 +8,7 @@ class Dram : public Storage /** * Constructor. * @param The number of `lines` contained in memory. The total number of - * words is this number multiplied by 4. + * words is this number multiplied by LINE_SIZE. * @param The number of clock cycles each access takes. * @return A new memory object. */ diff --git a/inc/storage.h b/inc/storage.h index 5ad4f99..c0f09a3 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -1,5 +1,6 @@ #ifndef STORAGE_H #define STORAGE_H +#include "definitions.h" #include "response.h" #include #include @@ -37,13 +38,13 @@ class Storage * @return A matrix of data values, where each row is a line and each column * is a word. */ - std::vector> view(int base, int lines); + std::vector> view(int base, int lines); protected: /** * The data currently stored in this level of storage. */ - std::vector> *data; + std::vector> *data; /** * A pointer to the next lowest level of storage. * Used in case of cache misses. diff --git a/src/storage/cache.cc b/src/storage/cache.cc index a4df820..f4f60ba 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -1,10 +1,11 @@ #include "cache.h" +#include "definitions.h" #include "response.h" #include Cache::Cache(int lines, Storage *lower, int delay) { - this->data = new std::vector>; + this->data = new std::vector>; this->data->resize(lines); this->lower = lower; this->delay = delay; diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 89c7316..845db21 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -1,10 +1,11 @@ #include "dram.h" +#include "definitions.h" #include "response.h" #include Dram::Dram(int lines, int delay) { - this->data = new std::vector>; + this->data = new std::vector>; this->data->resize(lines); this->delay = delay; this->lower = nullptr; @@ -14,7 +15,14 @@ Dram::~Dram() { delete this->data; } Response *Dram::write(Accessor accessor, signed int data, int address) { - return new Response(); + struct Response *r = new Response(); + int line = address / LINE_SIZE; + int word = address % LINE_SIZE; + + this->data->at(line).at(word) = data; + + r->status = OK; + return r; } Response *Dram::read(Accessor accessor, int address) { return nullptr; } diff --git a/src/storage/storage.cc b/src/storage/storage.cc index 49d8e7e..a9a883a 100644 --- a/src/storage/storage.cc +++ b/src/storage/storage.cc @@ -1,10 +1,12 @@ #include "storage.h" +#include "definitions.h" #include -std::vector> Storage::view(int base, int lines) +std::vector> +Storage::view(int base, int lines) { - base = (base / 4) * 4; - std::vector> ret(lines + 1); + base = (base / LINE_SIZE) * LINE_SIZE; + std::vector> ret(lines + 1); std::copy( this->data->begin() + base, this->data->begin() + base + lines, ret.begin()); diff --git a/tests/cache.cc b/tests/cache.cc index 3b3787d..3c1fba6 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -1,11 +1,12 @@ #include "cache.h" +#include "definitions.h" #include -TEST_CASE("Constructor initialize test 1", "[cache]") +TEST_CASE("Constructor singleton dram", "[cache]") { - Cache *c = new Cache(1, nullptr, 4); - std::array expected = {0, 0, 0, 0}; - std::array actual = c->view(0, 1)[0]; - CHECK(expected == actual); + Cache *c = new Cache(1, nullptr, LINE_SIZE); + std::array expected = {0, 0, 0, 0}; + std::array actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); delete c; } diff --git a/tests/dram.cc b/tests/dram.cc index 8d5d03b..15e2990 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -1,12 +1,34 @@ #include "dram.h" +#include "definitions.h" #include #include -TEST_CASE("Constructor initialize test 1", "[dram]") +TEST_CASE("Construct singleton dram", "[dram]") { - Dram *d = new Dram(1, 4); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Dram *d = new Dram(1, 1); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + delete d; +} + +TEST_CASE("Construct ingleton dram, store 0th element in zero cycles", "[dram]") +{ + Dram *d = new Dram(1, 0); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; CHECK(expected == actual); + + signed int w = 0x11223344; + + Response *r = d->write(MEMORY, w, 0x00000000); + REQUIRE(r->status == OK); + + + expected.at(0) = w; + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete r; delete d; } -- cgit v1.2.3 From 3221a2c310afb6ed124d6b67afda110d4b8dcade Mon Sep 17 00:00:00 2001 From: bd Date: Thu, 6 Mar 2025 01:35:27 -0500 Subject: Allow sidedoor free access to writing memory --- inc/storage.h | 9 +++++++-- src/storage/dram.cc | 31 ++++++++++++++++--------------- src/storage/storage.cc | 9 +++++++++ tests/dram.cc | 39 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 71 insertions(+), 17 deletions(-) (limited to 'src/storage/storage.cc') diff --git a/inc/storage.h b/inc/storage.h index f5659c5..841c531 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -11,6 +11,7 @@ enum Accessor { FETCH, L1CACHE, IDLE, + SIDE, }; class Storage @@ -21,7 +22,7 @@ class Storage * @param the source making the request. * @param the data (hexadecimal) to write. * @param the address to write to. - * @return a status code reflecting the state of the storage level. + * @return a status code reflecting the state of the request. */ virtual Response * write(Accessor accessor, signed int data, int address) = 0; @@ -29,7 +30,7 @@ class Storage * Get the data at `address`. * @param the source making the request. * @param the address being accessed. - * @return a status code reflecting the state of the storage level, and the + * @return a status code reflecting the state of the request, and the * data being returned. */ virtual Response *read(Accessor accessor, int address) = 0; @@ -43,6 +44,10 @@ class Storage std::vector> view(int base, int lines); protected: + /** + * Helper for `write`. + */ + void do_write(signed int, int); /** * The data currently stored in this level of storage. */ diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 3143a61..3eb0748 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -19,22 +19,23 @@ Response *Dram::write(Accessor accessor, signed int data, int address) struct Response *r = new Response(); r->status = WAIT; - /* Do this first--then process the first cycle immediately. */ - if (this->servicing == IDLE) { - this->servicing = accessor; - this->wait_time = delay; - } - - if (this->servicing == accessor) { - if (this->wait_time == 0) { - int line = address / LINE_SIZE; - int word = address % LINE_SIZE; + if (accessor == SIDE) { + this->do_write(data, address); + r->status = OK; + } else { + /* Do this first--then process the first cycle immediately. */ + if (this->servicing == IDLE) { + this->servicing = accessor; + this->wait_time = delay; + } - this->servicing = IDLE; - this->data->at(line).at(word) = data; - r->status = OK; - } else { - --this->wait_time; + if (this->servicing == accessor) { + if (this->wait_time == 0) { + this->do_write(data, address); + r->status = OK; + } else { + --this->wait_time; + } } } diff --git a/src/storage/storage.cc b/src/storage/storage.cc index a9a883a..024699b 100644 --- a/src/storage/storage.cc +++ b/src/storage/storage.cc @@ -12,3 +12,12 @@ Storage::view(int base, int lines) ret.begin()); return ret; } + +void Storage::do_write(signed data, int address) +{ + int line = address / LINE_SIZE; + int word = address % LINE_SIZE; + + this->servicing = IDLE; + this->data->at(line).at(word) = data; +} diff --git a/tests/dram.cc b/tests/dram.cc index 55d4d24..e98abc1 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -234,3 +234,42 @@ TEST_CASE( delete d; } + +TEST_CASE( + "Sidedoor bypasses delay", + "[dram]") +{ + Dram *d = new Dram(1, 3); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w1 = 0x11223344; + signed int w2 = 0x55667788; + + // MEMORY CYCLE 1 + Response *r = d->write(MEMORY, w1, 0x00000000); + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + REQUIRE(r->status == WAIT); + delete r; + + // MEMORY CYCLE 2 + actual = d->view(0, 1)[0]; + r = d->write(MEMORY, w1, 0x00000000); + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + REQUIRE(r->status == WAIT); + delete r; + // SIDE CYCLE 1 + r = d->write(SIDE, w2, 0x00000001); + actual = d->view(0, 1)[0]; + REQUIRE(r->status == OK); + delete r; + + expected.at(1) = w2; + actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + delete d; +} -- cgit v1.2.3 From 2c424d29fd813b1fbef3b07595713611a1684903 Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 8 Mar 2025 12:51:01 -0500 Subject: enforce single unit per clock cycle, order to serve storage requests --- inc/storage.h | 31 +++++- src/storage/dram.cc | 12 +-- src/storage/storage.cc | 11 ++- tests/dram.cc | 256 +++++++++++++++++++++++++++---------------------- 4 files changed, 180 insertions(+), 130 deletions(-) (limited to 'src/storage/storage.cc') diff --git a/inc/storage.h b/inc/storage.h index a38f17d..95b6749 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -2,18 +2,35 @@ #define STORAGE_H #include "definitions.h" #include "response.h" +#include #include -#include +#include #include enum Accessor { MEM, FETCH, L1CACHE, - IDLE, SIDE, }; +/** + * Wrapper class for std::deque. + * + * Implements a deque that does not push duplicate objects. + */ +template class Deque : public std::deque +{ + public: + using std::deque::deque; + + void push_back(const T &value) + { + if (std::find(this->begin(), this->end(), value) == this->end()) + std::deque::push_back(value); + } +}; + class Storage { public: @@ -41,6 +58,10 @@ class Storage * is a word. */ std::vector> view(int base, int lines); + /** + * Advances to the next job if the current job is completed. + */ + void resolve(); protected: /** @@ -62,11 +83,11 @@ class Storage */ int delay; /** - * The accessor currently being serviced. + * The accessors currently being serviced, in first come first serve order. */ - enum Accessor servicing; + Deque deque; /** - * The number of cycles until the currently request is completed. + * The number of cycles until the current request is completed. */ int wait_time; }; diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 4c4ca84..32f3fbb 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -2,14 +2,15 @@ #include "definitions.h" #include "response.h" #include +#include Dram::Dram(int lines, int delay) { this->data = new std::vector>; this->data->resize(lines); this->delay = delay; + this->wait_time = this->delay; this->lower = nullptr; - this->servicing = IDLE; } Dram::~Dram() { delete this->data; } @@ -23,17 +24,12 @@ Response Dram::write(Accessor accessor, signed int data, int address) r = OK; } else { /* Do this first--then process the first cycle immediately. */ - if (this->servicing == IDLE) { - this->servicing = accessor; - this->wait_time = delay; - } + this->deque.push_back(accessor); - if (this->servicing == accessor) { + if (this->deque.front() == accessor) { if (this->wait_time == 0) { this->do_write(data, address); r = OK; - } else { - --this->wait_time; } } } diff --git a/src/storage/storage.cc b/src/storage/storage.cc index 024699b..429ac2b 100644 --- a/src/storage/storage.cc +++ b/src/storage/storage.cc @@ -18,6 +18,15 @@ void Storage::do_write(signed data, int address) int line = address / LINE_SIZE; int word = address % LINE_SIZE; - this->servicing = IDLE; this->data->at(line).at(word) = data; } + +void Storage::resolve() +{ + if (this->wait_time == 0) { + this->deque.pop_front(); + this->wait_time = delay; + } else { + --this->wait_time; + } +} diff --git a/tests/dram.cc b/tests/dram.cc index ba81508..e0189c7 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -23,7 +23,7 @@ TEST_CASE( signed int w = 0x11223344; Response r = d->write(MEM, w, 0x00000000); - REQUIRE(r == OK); + CHECK(r == OK); expected.at(0) = w; actual = d->view(0, 1)[0]; @@ -35,34 +35,28 @@ TEST_CASE( TEST_CASE( "Construct singleton dram, store 0th element in three cycles", "[dram]") { - Dram *d = new Dram(1, 3); + int delay = 3; + Dram *d = new Dram(1, delay); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; CHECK(expected == actual); signed int w = 0x11223344; - // MEMORY CYCLE 1 - Response r = d->write(MEM, w, 0x00000000); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); + int i; + Response r; + for (i = 0; i < delay; ++i) { + r = d->write(MEM, w, 0x00000000); + CHECK(r == WAIT); - // MEMORY CYCLE 2 - r = d->write(MEM, w, 0x00000000); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } - // MEMORY CYCLE 3 r = d->write(MEM, w, 0x00000000); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); - - // MEMORY CYCLE 4 - r = d->write(MEM, w, 0x00000000); - REQUIRE(r == OK); + CHECK(r == OK); + d->resolve(); expected.at(0) = w; actual = d->view(0, 1)[0]; @@ -76,66 +70,58 @@ TEST_CASE( "conflict", "[dram]") { - Dram *d = new Dram(1, 3); + int delay = 3; + Dram *d = new Dram(1, delay); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; CHECK(expected == actual); - signed int w1 = 0x11223344; - signed int w2 = 0x55667788; + signed int w = 0x11223344; - // MEMORY CYCLE 1 - Response r = d->write(MEM, w1, 0x00000000); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); + int i; + Response r; + for (i = 0; i < delay; ++i) { + r = d->write(MEM, w, 0x00000000); + CHECK(r == WAIT); - // MEMORY CYCLE 2 - actual = d->view(0, 1)[0]; - r = d->write(MEM, w1, 0x00000000); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); + actual = d->view(0, 1)[0]; + CHECK(r == WAIT); - // MEMORY CYCLE 3 - r = d->write(MEM, w1, 0x00000000); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); + REQUIRE(expected == actual); + d->resolve(); + } - // MEMORY CYCLE 4 - r = d->write(MEM, w1, 0x00000000); + r = d->write(MEM, w, 0x00000000); REQUIRE(r == OK); - // NOTE: servicing on the same clock cycle should probably not be allowed - // FETCH CYCLE 1 - r = d->write(FETCH, w2, 0x00000001); - actual = d->view(0, 1)[0]; - REQUIRE(r == WAIT); + // clock cycle did NOT resolve yet! + // this fetch should not make progress + r = d->write(FETCH, w, 0x00000001); + CHECK(r == WAIT); - expected.at(0) = w1; actual = d->view(0, 1)[0]; - CHECK(expected == actual); + CHECK(r == WAIT); + d->resolve(); - // FETCH CYCLE 2 - r = d->write(FETCH, w2, 0x00000001); + expected.at(0) = w; actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - REQUIRE(r == WAIT); - // FETCH CYCLE 3 - r = d->write(FETCH, w2, 0x00000001); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); + for (i = 0; i < delay; ++i) { + r = d->write(FETCH, w, 0x00000001); + CHECK(r == WAIT); - // FETCH CYCLE 4 - r = d->write(FETCH, w2, 0x00000001); + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } + + r = d->write(FETCH, w, 0x00000001); actual = d->view(0, 1)[0]; - REQUIRE(r == OK); + CHECK(r == OK); - expected.at(1) = w2; + expected.at(1) = w; actual = d->view(0, 1)[0]; - CHECK(expected == actual); + REQUIRE(expected == actual); delete d; } @@ -145,103 +131,141 @@ TEST_CASE( "conflict", "[dram]") { - Dram *d = new Dram(1, 3); + int delay = 2; + Dram *d = new Dram(1, 2); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; CHECK(expected == actual); - signed int w1 = 0x11223344; - signed int w2 = 0x55667788; + signed int w = 0x11223344; - // MEMORY CYCLE 1 - Response r = d->write(MEM, w1, 0x00000000); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); + int i; + Response r; + for (i = 0; i < delay; ++i) { + r = d->write(MEM, w, 0x00000000); + CHECK(r == WAIT); + + r = d->write(FETCH, w, 0x00000001); + CHECK(r == WAIT); + + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } + + r = d->write(MEM, w, 0x00000000); + CHECK(r == OK); + r = d->write(FETCH, w, 0x00000001); + CHECK(r == WAIT); + d->resolve(); - // MEMORY CYCLE 2 - actual = d->view(0, 1)[0]; - r = d->write(MEM, w1, 0x00000000); actual = d->view(0, 1)[0]; + expected.at(0) = w; REQUIRE(expected == actual); - REQUIRE(r == WAIT); - // FETCH CYCLE 1 - r = d->write(FETCH, w2, 0x00000001); + + for (i = 0; i < delay; ++i) { + r = d->write(FETCH, w, 0x00000001); + CHECK(r == WAIT); + + r = d->write(MEM, w, 0x00000003); + CHECK(r == WAIT); + + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } + + r = d->write(FETCH, w, 0x00000001); actual = d->view(0, 1)[0]; - REQUIRE(r == WAIT); + CHECK(r == OK); + r = d->write(MEM, w, 0x00000003); + CHECK(r == WAIT); - r = d->write(MEM, w1, 0x00000000); + expected.at(1) = w; actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - REQUIRE(r == WAIT); - // FETCH CYCLE 1 - r = d->write(FETCH, w2, 0x00000001); - actual = d->view(0, 1)[0]; - REQUIRE(r == WAIT); - r = d->write(MEM, w1, 0x00000000); - REQUIRE(r == OK); - // NOTE: servicing on the same clock cycle should probably not be allowed - // FETCH CYCLE 1 - r = d->write(FETCH, w2, 0x00000001); - actual = d->view(0, 1)[0]; - REQUIRE(r == WAIT); + delete d; +} - expected.at(0) = w1; - actual = d->view(0, 1)[0]; +TEST_CASE("Many conflicting requests first-come first serve", "[dram]") +{ + int delay = 1; + Dram *d = new Dram(1, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; CHECK(expected == actual); - r = d->write(FETCH, w2, 0x00000001); + signed int w = 0x11223344; + + Response r; + r = d->write(FETCH, w, 0x00000000); + r = d->write(MEM, w, 0x00000001); + actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - REQUIRE(r == WAIT); + d->resolve(); - r = d->write(FETCH, w2, 0x00000001); + r = d->write(FETCH, w, 0x00000000); + r = d->write(L1CACHE, w, 0x00000002); + // call mem after cache + r = d->write(MEM, w, 0x00000001); + + expected.at(0) = w; actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - REQUIRE(r == WAIT); + d->resolve(); + + r = d->write(MEM, w, 0x00000001); + r = d->write(L1CACHE, w, 0x00000002); - r = d->write(FETCH, w2, 0x00000001); actual = d->view(0, 1)[0]; - REQUIRE(r == OK); + REQUIRE(expected == actual); + d->resolve(); - expected.at(1) = w2; + r = d->write(MEM, w, 0x00000001); + r = d->write(L1CACHE, w, 0x00000002); + + expected.at(1) = w; actual = d->view(0, 1)[0]; - CHECK(expected == actual); + REQUIRE(expected == actual); delete d; } TEST_CASE("Sidedoor bypasses delay", "[dram]") { - Dram *d = new Dram(1, 3); + int delay = 3; + Dram *d = new Dram(1, delay); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; CHECK(expected == actual); - signed int w1 = 0x11223344; - signed int w2 = 0x55667788; + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay - 1; ++i) { + r = d->write(MEM, w, 0x00000000); + CHECK(r == WAIT); - // MEMORY CYCLE 1 - Response r = d->write(MEM, w1, 0x00000000); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - REQUIRE(r == WAIT); + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } - // MEMORY CYCLE 2 - actual = d->view(0, 1)[0]; - r = d->write(MEM, w1, 0x00000000); + r = d->write(MEM, w, 0x00000000); + CHECK(r == WAIT); actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - REQUIRE(r == WAIT); - // SIDE CYCLE 1 - r = d->write(SIDE, w2, 0x00000001); + + r = d->write(SIDE, w, 0x00000001); actual = d->view(0, 1)[0]; - REQUIRE(r == OK); + CHECK(r == OK); - expected.at(1) = w2; + expected.at(1) = w; actual = d->view(0, 1)[0]; - CHECK(expected == actual); + REQUIRE(expected == actual); delete d; } -- cgit v1.2.3 From 6470c93a411dd8f64a91a7812274349b258a9957 Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 8 Mar 2025 13:47:22 -0500 Subject: Fix bug where wait_time would decrease while idle --- src/storage/dram.cc | 1 - src/storage/storage.cc | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/storage/storage.cc') diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 32f3fbb..5b4c63b 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -2,7 +2,6 @@ #include "definitions.h" #include "response.h" #include -#include Dram::Dram(int lines, int delay) { diff --git a/src/storage/storage.cc b/src/storage/storage.cc index 429ac2b..429f8aa 100644 --- a/src/storage/storage.cc +++ b/src/storage/storage.cc @@ -26,7 +26,7 @@ void Storage::resolve() if (this->wait_time == 0) { this->deque.pop_front(); this->wait_time = delay; - } else { + } else if (!this->deque.empty()) { --this->wait_time; } } -- cgit v1.2.3 From c4c985bfffca6f4b7dc9e08e275837f2b213b593 Mon Sep 17 00:00:00 2001 From: bd Date: Sat, 8 Mar 2025 15:19:57 -0500 Subject: Remove queue in storage.h --- inc/storage.h | 23 +++-------------------- src/storage/dram.cc | 5 +++-- src/storage/storage.cc | 4 ++-- tests/dram.cc | 45 --------------------------------------------- 4 files changed, 8 insertions(+), 69 deletions(-) (limited to 'src/storage/storage.cc') diff --git a/inc/storage.h b/inc/storage.h index 95b6749..4bf4591 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -4,33 +4,16 @@ #include "response.h" #include #include -#include #include enum Accessor { + IDLE, MEM, FETCH, L1CACHE, SIDE, }; -/** - * Wrapper class for std::deque. - * - * Implements a deque that does not push duplicate objects. - */ -template class Deque : public std::deque -{ - public: - using std::deque::deque; - - void push_back(const T &value) - { - if (std::find(this->begin(), this->end(), value) == this->end()) - std::deque::push_back(value); - } -}; - class Storage { public: @@ -83,9 +66,9 @@ class Storage */ int delay; /** - * The accessors currently being serviced, in first come first serve order. + * The accessor currently being serviced. */ - Deque deque; + enum Accessor requester; /** * The number of cycles until the current request is completed. */ diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 5b4c63b..7197668 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -23,9 +23,10 @@ Response Dram::write(Accessor accessor, signed int data, int address) r = OK; } else { /* Do this first--then process the first cycle immediately. */ - this->deque.push_back(accessor); + if (this->requester == IDLE) + this->requester = accessor; - if (this->deque.front() == accessor) { + if (this->requester == accessor) { if (this->wait_time == 0) { this->do_write(data, address); r = OK; diff --git a/src/storage/storage.cc b/src/storage/storage.cc index 429f8aa..e3067a2 100644 --- a/src/storage/storage.cc +++ b/src/storage/storage.cc @@ -24,9 +24,9 @@ void Storage::do_write(signed data, int address) void Storage::resolve() { if (this->wait_time == 0) { - this->deque.pop_front(); + this->requester = IDLE; this->wait_time = delay; - } else if (!this->deque.empty()) { + } else if (this->requester != IDLE) { --this->wait_time; } } diff --git a/tests/dram.cc b/tests/dram.cc index e0189c7..c646135 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -188,51 +188,6 @@ TEST_CASE( delete d; } -TEST_CASE("Many conflicting requests first-come first serve", "[dram]") -{ - int delay = 1; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223344; - - Response r; - r = d->write(FETCH, w, 0x00000000); - r = d->write(MEM, w, 0x00000001); - - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - d->resolve(); - - r = d->write(FETCH, w, 0x00000000); - r = d->write(L1CACHE, w, 0x00000002); - // call mem after cache - r = d->write(MEM, w, 0x00000001); - - expected.at(0) = w; - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - d->resolve(); - - r = d->write(MEM, w, 0x00000001); - r = d->write(L1CACHE, w, 0x00000002); - - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - d->resolve(); - - r = d->write(MEM, w, 0x00000001); - r = d->write(L1CACHE, w, 0x00000002); - - expected.at(1) = w; - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - - delete d; -} - TEST_CASE("Sidedoor bypasses delay", "[dram]") { int delay = 3; -- cgit v1.2.3