From 1e1279817e8a2a03b8c1acb9425464c82a065e01 Mon Sep 17 00:00:00 2001 From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com> Date: Tue, 11 Mar 2025 01:31:43 -0400 Subject: Write line, dirty cache eviction, cache load word/line (for future multilevel cache implementation) --- src/storage/cache.cc | 49 ++++++++++++++++++++++++++++++++++++++++++------- src/storage/dram.cc | 22 +++++++++++++--------- 2 files changed, 55 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 1a8a10b..66603e2 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -49,10 +49,43 @@ Response Cache::write(Accessor accessor, signed int data, int address) return r; } -Response Cache::read( - Accessor accessor, int address, std::array &data) +// TODO: tests for multi level cache +Response Cache::read(Accessor accessor, int address, std::array &data) { - return WAIT; + Response r = WAIT; + if (this->requester == IDLE) + this->requester = accessor; + if (this->requester == accessor) { + fetch_resource(address); + if (this->is_waiting) + r = BLOCKED; + else if (this->wait_time == 0) { + int tag, index, offset; + get_bit_fields(address, &tag, &index, &offset); + data = this->data->at(index); + r = OK; + } + } + return r; +} + +Response Cache::read_word(Accessor accessor, int address, signed int &data) +{ + Response r = WAIT; + if (this->requester == IDLE) + this->requester = accessor; + if (this->requester == accessor) { + fetch_resource(address); + if (this->is_waiting) + r = BLOCKED; + else if (this->wait_time == 0) { + int tag, index, offset; + get_bit_fields(address, &tag, &index, &offset); + data = this->data->at(index)->at(offset); + r = OK; + } + } + return r; } void Cache::fetch_resource(int expected) @@ -64,19 +97,21 @@ void Cache::fetch_resource(int expected) get_bit_fields(expected, &tag, &index, &offset); meta = &this->meta.at(index); + actual = this->data->at(index); if (meta->at(0) != tag) { // address not in cache if (meta->at(1) >= 0) { // occupant is dirty - // TODO - r = WAIT; + // writing line to DRam in case of dirty cache eviction + r = this->lower->write_line(L1CACHE, actual, ((index << LINE_SPEC) + (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC)))); + if (r == OK) { + meta->at(1) = -1; + } } else { - actual = this->data->at(index); r = this->lower->read(L1CACHE, expected, actual); if (r == OK) { meta->at(0) = tag; - meta->at(1) = -1; } } } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index e755c2a..290d38b 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -28,6 +28,18 @@ void Dram::do_write(signed data, int address) this->data->at(line).at(word) = data; } +void Dram::do_read(std::array &data_line, int address) +{ + int line = address / LINE_SIZE; + data_line = this->data->at(line); +} + +void Dram::write_line(std::array data_line, int address){ + int line = address / LINE_SIZE; + this->data->at(line) = data_line; +} + + Response Dram::write(Accessor accessor, signed int data, int address) { Response r = WAIT; @@ -51,15 +63,7 @@ Response Dram::write(Accessor accessor, signed int data, int address) return r; } -void Dram::do_read(std::array &data_line, int address) -{ - int line = address / LINE_SIZE; - data_line = this->data->at(line); -} - -Response Dram::read( - Accessor accessor, int address, std::array &data) -{ +Response Dram::read(Accessor accessor, int address, std::array& data) { Response r = WAIT; if (this->requester == IDLE) -- cgit v1.2.3 From 93b010dbbcdc921bfccae673918eb9fbf354538a Mon Sep 17 00:00:00 2001 From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com> Date: Tue, 11 Mar 2025 11:18:01 -0400 Subject: support for reading word, writing line to storage, dirty cache eviction, cache load --- inc/cache.h | 3 ++- inc/dram.h | 17 ++++++++++++++--- inc/storage.h | 17 +++++++++++++++-- src/storage/cache.cc | 30 ++++++++++++++++++++++++++--- src/storage/dram.cc | 54 +++++++++++++++++++++++++++++++++++++++++++++++++--- tests/dram.cc | 2 +- 6 files changed, 110 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/inc/cache.h b/inc/cache.h index 5cdcea4..bc37f54 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -21,11 +21,12 @@ class Cache : public Storage ~Cache(); Response write(Accessor accessor, signed int data, int address) override; + Response write_line(Accessor accessor, std::array data_line, int address) override; Response read( Accessor accessor, int address, std::array &data) override; - Response read_word(Accessor accessor, int address, signed int &data); + Response read_word(Accessor accessor, int address, signed int &data) override; /** * Getter for the meta attribute. diff --git a/inc/dram.h b/inc/dram.h index d68797f..427500c 100644 --- a/inc/dram.h +++ b/inc/dram.h @@ -22,18 +22,29 @@ class Dram : public Storage Accessor accessor, int address, std::array &data) override; + Response write_line(Accessor accessor, std::array data_line, int address) override; - void write_line(std::array data_line, int address); + Response read(Accessor accessor, int address, std::array& data) override; + Response read_word(Accessor accessor, int address, signed int &data) override; private: /** - * Helper for `write`. + * Helper for `write` a word */ void do_write(signed int, int); /** - * Helper for `read`. + * Helper for writing a line. + */ + void do_write_line(std::array data_line, int address); + /** + * Helper for `read` a line */ void do_read(std::array &data_line, int address); + void do_read(std::array& data_line, int address); + /** + * Helper for reading a word. + */ + void do_read_word(signed int &data, int address); }; std::ostream &operator<<(std::ostream &os, const Dram &d); diff --git a/inc/storage.h b/inc/storage.h index a30e74d..fc93d7a 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -14,15 +14,22 @@ class Storage virtual ~Storage() = default; /** - * Write `data` into `address`. + * Write `data` word into `address`. * @param the source making the request. * @param the data (hexadecimal) to write. * @param the address to write to. * @return a status code reflecting the state of the request. */ virtual Response write(Accessor accessor, signed int data, int address) = 0; + + /** + * Write a data line to given address in this level of storage + */ + virtual Response write_line(Accessor accessor, std::array data_line, int address) = 0; + + /** - * Get the data at `address`. + * Get the data line at `address`. * @param the source making the request. * @param the address being accessed. * @return a status code reflecting the state of the request, and the @@ -32,6 +39,12 @@ class Storage Accessor accessor, int address, std::array &data) = 0; + + /** + * Read a word from given address in this level of storage + */ + virtual Response read_word(Accessor accessor, int address, signed int &data) = 0; + /** * Sidedoor view of `lines` of memory starting at `base`. * @param The base line to start getting memory from. diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 66603e2..08699ed 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -49,8 +49,32 @@ Response Cache::write(Accessor accessor, signed int data, int address) return r; } +Response Cache::write_line(Accessor accessor, std::array data_line, int address) +{ + Response r = WAIT; + + /* Do this first--then process the first cycle immediately. */ + if (this->requester == IDLE) + this->requester = accessor; + + if (this->requester == accessor) { + fetch_resource(address); + if (this->is_waiting) + r = BLOCKED; + else if (this->wait_time == 0) { + int tag, index, offset; + get_bit_fields(address, &tag, &index, &offset); + this->data->at(index) = data_line; + this->meta[index].at(1) = 1; + r = OK; + } + } + + return r; +} + // TODO: tests for multi level cache -Response Cache::read(Accessor accessor, int address, std::array &data) +Response Cache::read(Accessor accessor, int address, std::array &data_line) { Response r = WAIT; if (this->requester == IDLE) @@ -62,7 +86,7 @@ Response Cache::read(Accessor accessor, int address, std::arraywait_time == 0) { int tag, index, offset; get_bit_fields(address, &tag, &index, &offset); - data = this->data->at(index); + data_line = this->data->at(index); r = OK; } } @@ -81,7 +105,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data) else if (this->wait_time == 0) { int tag, index, offset; get_bit_fields(address, &tag, &index, &offset); - data = this->data->at(index)->at(offset); + data = this->data->at(index).at(offset); r = OK; } } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 290d38b..be360a4 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -20,7 +20,7 @@ Dram::Dram(int lines, int delay) Dram::~Dram() { delete this->data; } -void Dram::do_write(signed data, int address) +void Dram::do_write(signed int data, int address) { int line = address / LINE_SIZE; int word = address % LINE_SIZE; @@ -28,15 +28,46 @@ void Dram::do_write(signed data, int address) this->data->at(line).at(word) = data; } +void Dram::do_write_line(std::array data_line, int address){ + int line = address / LINE_SIZE; + this->data->at(line) = data_line; +} + void Dram::do_read(std::array &data_line, int address) { int line = address / LINE_SIZE; data_line = this->data->at(line); } -void Dram::write_line(std::array data_line, int address){ +void Dram::do_read_word(signed int &data, int address) +{ int line = address / LINE_SIZE; - this->data->at(line) = data_line; + int word = address % LINE_SIZE; + data = this->data->at(line).at(word); +} + + + +Response Dram::write_line(Accessor accessor, std::array data_line, int address) +{ + Response r = WAIT; + + if (accessor == SIDE) { + this->do_write_line(data_line, address); + r = OK; + } else { + /* Do this first--then process the first cycle immediately. */ + if (this->requester == IDLE) + this->requester = accessor; + + if (this->requester == accessor) { + if (this->wait_time == 0) { + this->do_write_line(data_line, address); + r = OK; + } + } + } + return r; } @@ -79,6 +110,22 @@ Response Dram::read(Accessor accessor, int address, std::arrayrequester == IDLE) + this->requester = accessor; + + if (this->requester == accessor) { + if (this->wait_time == 0) { + this->do_read_word(data, address); + r = OK; + } + } + + return r; +} + std::ostream &operator<<(std::ostream &os, const Dram &d) { const auto default_flags = std::cout.flags(); @@ -102,3 +149,4 @@ std::ostream &operator<<(std::ostream &os, const Dram &d) std::cout.fill(default_fill); return os; } + diff --git a/tests/dram.cc b/tests/dram.cc index ff0d860..7b19ac4 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -196,7 +196,7 @@ TEST_CASE("Construct singleton dram, write a line to an address", "[dram]") signed int w = 0x11223311; expected = {w, w+1, w+2, w+3}; int addr = 0x00000000; - d->write_line(expected, addr); + d->write_line(MEM, expected, addr); Response r = d->read(MEM, 0x00000000, actual); CHECK(r == OK); -- cgit v1.2.3 From e06f97b02b161f5356117d0ccc5a9ea9b11fe99e Mon Sep 17 00:00:00 2001 From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com> Date: Tue, 11 Mar 2025 11:45:50 -0400 Subject: Resolving conflicts --- inc/cache.h | 2 +- inc/dram.h | 5 +---- src/storage/dram.cc | 4 ++-- 3 files changed, 4 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/inc/cache.h b/inc/cache.h index bc37f54..20a40c2 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -25,7 +25,7 @@ class Cache : public Storage Response read( Accessor accessor, int address, - std::array &data) override; + std::array &data_line) override; Response read_word(Accessor accessor, int address, signed int &data) override; /** diff --git a/inc/dram.h b/inc/dram.h index 427500c..7774040 100644 --- a/inc/dram.h +++ b/inc/dram.h @@ -21,10 +21,8 @@ class Dram : public Storage Response read( Accessor accessor, int address, - std::array &data) override; + std::array &data_line) override; Response write_line(Accessor accessor, std::array data_line, int address) override; - - Response read(Accessor accessor, int address, std::array& data) override; Response read_word(Accessor accessor, int address, signed int &data) override; private: @@ -40,7 +38,6 @@ class Dram : public Storage * Helper for `read` a line */ void do_read(std::array &data_line, int address); - void do_read(std::array& data_line, int address); /** * Helper for reading a word. */ diff --git a/src/storage/dram.cc b/src/storage/dram.cc index be360a4..76c4f90 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -94,7 +94,7 @@ Response Dram::write(Accessor accessor, signed int data, int address) return r; } -Response Dram::read(Accessor accessor, int address, std::array& data) { +Response Dram::read(Accessor accessor, int address, std::array& data_line) { Response r = WAIT; if (this->requester == IDLE) @@ -102,7 +102,7 @@ Response Dram::read(Accessor accessor, int address, std::arrayrequester == accessor) { if (this->wait_time == 0) { - this->do_read(data, address); + this->do_read(data_line, address); r = OK; } } -- cgit v1.2.3 From fdb15ea8595d7c702d7577e86a1a96adc6ecdf81 Mon Sep 17 00:00:00 2001 From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com> Date: Tue, 11 Mar 2025 15:24:57 -0400 Subject: Tests for write line in Dram, memory address wrapping implementation and tests --- inc/utils.h | 2 + src/utils/utils.cc | 7 ++ tests/dram.cc | 336 ++++++++++++++++++++++++++++++++++++++++++++++++++++- tests/utils.cc | 42 +++++++ 4 files changed, 386 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/inc/utils.h b/inc/utils.h index 71e515b..aa8831b 100644 --- a/inc/utils.h +++ b/inc/utils.h @@ -20,4 +20,6 @@ void get_bit_fields(int address, int *tag, int *index, int *offset); */ const std::string string_format(const char *const zcFormat, ...); +int wrap_address(int address); + #endif /* UTILS_H_INCLUDED */ diff --git a/src/utils/utils.cc b/src/utils/utils.cc index 5de8e89..f95d88f 100644 --- a/src/utils/utils.cc +++ b/src/utils/utils.cc @@ -28,3 +28,10 @@ const std::string string_format(const char *const zcFormat, ...) va_end(vaArgs); return std::string(zc.data(), iLen); } + +int wrap_address(int address) { + if (address < 0){ + return ((address % MEM_SIZE) + MEM_SIZE) % MEM_SIZE; + } + return address % MEM_SIZE; +} diff --git a/tests/dram.cc b/tests/dram.cc index 7b19ac4..8425d3b 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -186,7 +186,187 @@ TEST_CASE( delete d; } -TEST_CASE("Construct singleton dram, write a line to an address", "[dram]") +TEST_CASE( + "Construct singleton dram, store line in zero cycles", "[dram]") +{ + Dram *d = new Dram(1, 0); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + expected = {w, w+1, w+2, w+3}; + + Response r = d->write_line(MEM, expected, 0x00000000); + CHECK(r == OK); + + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; +} + +TEST_CASE( + "Construct singleton dram, store line in three cycles", "[dram]") +{ + int delay = 3; + Dram *d = new Dram(1, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + std::array written_line = {w, w+1, w+2, w+3}; + + int i; + Response r; + for (i = 0; i < delay; ++i) { + r = d->write_line(MEM, written_line, 0x00000000); + CHECK(r == WAIT); + + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } + + r = d->write_line(MEM, written_line, 0x00000000); + CHECK(r == OK); + d->resolve(); + + expected = written_line; + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; +} + +TEST_CASE( + "Construct singleton dram, store line in three cycles no " + "conflict", + "[dram]") +{ + int delay = 3; + Dram *d = new Dram(1, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + std::array written_line = {w, w+1, w+2, w+3}; + + int i; + Response r; + for (i = 0; i < delay; ++i) { + r = d->write_line(MEM, written_line, 0x00000000); + CHECK(r == WAIT); + + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } + + r = d->write_line(MEM, written_line, 0x00000000); + REQUIRE(r == OK); + // clock cycle did NOT resolve yet! + // this fetch should not make progress + r = d->write_line(FETCH, written_line, 0x00000001); + CHECK(r == WAIT); + + actual = d->view(0, 1)[0]; + CHECK(r == WAIT); + d->resolve(); + + expected = written_line; + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + + written_line = {w+4, w+5, w+6, w+7}; + + for (i = 0; i < delay; ++i) { + r = d->write_line(FETCH, written_line, 0x00000001); + CHECK(r == WAIT); + + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } + + r = d->write_line(FETCH, written_line, 0x00000001); + actual = d->view(0, 1)[0]; + CHECK(r == OK); + + expected = written_line; + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; +} + +TEST_CASE( + "Construct singleton dram, store line in three cycles much " + "conflict", + "[dram]") +{ + int delay = 2; + Dram *d = new Dram(1, 2); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + std::array written_line = {w, w+1, w+2, w+3}; + + int i; + Response r; + for (i = 0; i < delay; ++i) { + r = d->write_line(MEM, written_line, 0x00000000); + CHECK(r == WAIT); + + r = d->write_line(FETCH, written_line, 0x00000001); + CHECK(r == WAIT); + + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } + + r = d->write_line(MEM, written_line, 0x00000000); + CHECK(r == OK); + r = d->write_line(FETCH, written_line, 0x00000001); + CHECK(r == WAIT); + d->resolve(); + + actual = d->view(0, 1)[0]; + expected = written_line; + REQUIRE(expected == actual); + + written_line = {w+4, w+5, w+6, w+7}; + for (i = 0; i < delay; ++i) { + r = d->write_line(FETCH, written_line, 0x00000001); + CHECK(r == WAIT); + + r = d->write_line(MEM, written_line, 0x00000003); + CHECK(r == WAIT); + + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + d->resolve(); + } + + r = d->write_line(FETCH, written_line, 0x00000001); + actual = d->view(0, 1)[0]; + CHECK(r == OK); + r = d->write_line(MEM, written_line, 0x00000003); + CHECK(r == WAIT); + + expected = written_line; + actual = d->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; +} + +TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, read in 0 cycles", "[dram]") { Dram *d = new Dram(1, 0); std::array expected = {0, 0, 0, 0}; @@ -217,6 +397,160 @@ TEST_CASE("Construct singleton dram, write a line to an address", "[dram]") delete d; } +TEST_CASE("Construct singleton dram, write a line to an address in three cycles, read it in three cycles", "[dram]") +{ + int delay = 3; + Dram *d = new Dram(1, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223311; + expected = {w, w+1, w+2, w+3}; + int addr = 0x00000000; + + int i; + Response r; + + for(i=0; iwrite_line(MEM, expected, addr); + d->resolve(); + } + r = d->write_line(MEM, expected, addr); + d->resolve(); + + for (i = 0; i < delay; ++i) { + r = d->read(MEM, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(MEM, 0x00000000, actual); + CHECK(r == OK); + d->resolve(); + REQUIRE(expected == actual); + delete d; +} + +TEST_CASE( + "Construct singleton dram, store line in 3 cycles, read line in 3 cycles with no conflict","[dram]") +{ + int delay = 3; + Dram *d = new Dram(1, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223311; + expected = {w, w+1, w+2, w+3}; + int addr = 0x00000000; + + int i; + Response r; + for(int j=0; jwrite_line(MEM, expected, addr); + d->resolve(); + } + r = d->write_line(MEM, expected, addr++); + d->resolve(); + + for (i = 0; i < delay; ++i) { + r = d->read(MEM, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(MEM, 0x00000000, actual); + REQUIRE(r == OK); + r = d->read(FETCH, 0x00000003, actual); + CHECK(r == WAIT); + d->resolve(); + REQUIRE(expected == actual); + + actual = {0,0,0,0}; + for (i = 0; i < delay; ++i) { + r = d->read(FETCH, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(FETCH, 0x00000000, actual); + REQUIRE(r == OK); + r = d->read(MEM, 0x00000002, actual); + CHECK(r == WAIT); + d->resolve(); + REQUIRE(expected == actual); + + delete d; + +} + +TEST_CASE( + "Construct singleton dram, store line in 3 cycles, read line in 3 cycles with much conflict","[dram]") +{ + int delay = 3; + Dram *d = new Dram(1, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223311; + expected = {w, w+1, w+2, w+3}; + int addr = 0x00000000; + + int i; + Response r; + for(int j=0; jwrite_line(MEM, expected, addr); + d->resolve(); + } + r = d->write_line(MEM, expected, addr++); + d->resolve(); + + + for (i = 0; i < delay; ++i) { + r = d->read(MEM, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + r = d->read(FETCH, 0x00000002, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(MEM, 0x00000000, actual); + REQUIRE(r == OK); + r = d->read(FETCH, 0x00000003, actual); + CHECK(r == WAIT); + d->resolve(); + REQUIRE(expected == actual); + + actual = {0,0,0,0}; + for (i = 0; i < delay; ++i) { + r = d->read(FETCH, 0x00000000, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + r = d->read(MEM, 0x00000002, actual); + CHECK(r == WAIT); + REQUIRE(expected != actual); + d->resolve(); + } + + r = d->read(FETCH, 0x00000000, actual); + REQUIRE(r == OK); + r = d->read(MEM, 0x00000002, actual); + CHECK(r == WAIT); + d->resolve(); + REQUIRE(expected == actual); + + delete d; + +} + + TEST_CASE("Construct singleton dram, write a line to an address one element at a time, read it in zero cycles", "[dram]") { Dram *d = new Dram(1, 0); diff --git a/tests/utils.cc b/tests/utils.cc index 5368204..f0e4c24 100644 --- a/tests/utils.cc +++ b/tests/utils.cc @@ -21,3 +21,45 @@ TEST_CASE("Parse arbitrary fields # two", "[cache]") CHECK(index == 0b01110); CHECK(offset == 0b11); } + +TEST_CASE("wrap address outside upper bound", "[utils]") +{ + int address = MEM_SIZE + 25; + int wrapped = wrap_address(address); + REQUIRE(wrapped == 25); +} + +TEST_CASE("wrap address inside upper bound", "[utils]") +{ + int address = MEM_SIZE - 25; + int wrapped = wrap_address(address); + REQUIRE(wrapped == MEM_SIZE - 25); +} + +TEST_CASE("wrap address at upper bound", "[utils]") +{ + int address = MEM_SIZE; + int wrapped = wrap_address(address); + REQUIRE(wrapped == 0); +} + +TEST_CASE("wrap address lower than 0 with magnitude lesser than mem size", "[utils]") +{ + int address = -10; + int wrapped = wrap_address(address); + REQUIRE(wrapped == MEM_SIZE - 10); +} + +TEST_CASE("wrap address lower than 0 but with magnitude greater than mem size", "[utils]") +{ + int address = -(MEM_SIZE + 10); + int wrapped = wrap_address(address); + REQUIRE(wrapped == MEM_SIZE - 10); +} + +TEST_CASE("wrap address at 0", "[utils]") +{ + int address = 0; + int wrapped = wrap_address(address); + REQUIRE(wrapped == 0); +} \ No newline at end of file -- cgit v1.2.3 From 07e0b709f35ee83d91c62dfbc9cb3f4de7e7ef98 Mon Sep 17 00:00:00 2001 From: Siddarth-Suresh <65844402+Siddarth-Suresh@users.noreply.github.com> Date: Tue, 11 Mar 2025 15:54:22 -0400 Subject: read has to wait until cache has the right line from memory after eviction, write only has to wait until eviction and does not care about line replacement in cache from memory --- inc/cache.h | 3 ++- inc/operation.h | 9 +++++++++ src/storage/cache.cc | 13 ++++++++----- 3 files changed, 19 insertions(+), 6 deletions(-) create mode 100644 inc/operation.h (limited to 'src') diff --git a/inc/cache.h b/inc/cache.h index 20a40c2..7a1a380 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -1,6 +1,7 @@ #ifndef CACHE_H #define CACHE_H #include "definitions.h" +#include "operation.h" #include "storage.h" #include #include @@ -42,7 +43,7 @@ class Cache : public Storage * cache level to true, and the victim line is chosen/written back. * @param the address that must be present in cache. */ - void fetch_resource(int address); + void fetch_resource(Operation op, int address); /** * An array of metadata about elements in `data`. * If the first value of an element is negative, the corresponding diff --git a/inc/operation.h b/inc/operation.h new file mode 100644 index 0000000..a35344e --- /dev/null +++ b/inc/operation.h @@ -0,0 +1,9 @@ +#ifndef OPERATION_H +#define OPERATION_H + +enum Operation { + READ, + WRITE +}; + +#endif /* OPERATION_H_INCLUDED */ \ No newline at end of file diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 08699ed..1224aa9 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -34,7 +34,7 @@ Response Cache::write(Accessor accessor, signed int data, int address) this->requester = accessor; if (this->requester == accessor) { - fetch_resource(address); + fetch_resource(WRITE,address); if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { @@ -58,7 +58,7 @@ Response Cache::write_line(Accessor accessor, std::array this->requester = accessor; if (this->requester == accessor) { - fetch_resource(address); + fetch_resource(WRITE,address); if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { @@ -80,7 +80,7 @@ Response Cache::read(Accessor accessor, int address, std::arrayrequester == IDLE) this->requester = accessor; if (this->requester == accessor) { - fetch_resource(address); + fetch_resource(READ,address); if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { @@ -99,7 +99,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data) if (this->requester == IDLE) this->requester = accessor; if (this->requester == accessor) { - fetch_resource(address); + fetch_resource(READ,address); if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { @@ -112,7 +112,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data) return r; } -void Cache::fetch_resource(int expected) +void Cache::fetch_resource(Operation op, int expected) { Response r = OK; int tag, index, offset; @@ -131,6 +131,9 @@ void Cache::fetch_resource(int expected) r = this->lower->write_line(L1CACHE, actual, ((index << LINE_SPEC) + (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC)))); if (r == OK) { meta->at(1) = -1; + if(op == READ){ + r = WAIT; //if operation is read, need to wait until cache is loaded with right value from memory address, if operation is write, then this is not necessary + } } } else { r = this->lower->read(L1CACHE, expected, actual); -- cgit v1.2.3 From 12a822e68b2e82d4b86888304f94b60752465a0a Mon Sep 17 00:00:00 2001 From: bd Date: Tue, 11 Mar 2025 16:30:40 -0400 Subject: remove operation.h and branch determined by read/write in cache load --- inc/cache.h | 3 +-- inc/operation.h | 9 --------- src/storage/cache.cc | 26 +++++++++++++++----------- 3 files changed, 16 insertions(+), 22 deletions(-) delete mode 100644 inc/operation.h (limited to 'src') diff --git a/inc/cache.h b/inc/cache.h index 7a1a380..20a40c2 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -1,7 +1,6 @@ #ifndef CACHE_H #define CACHE_H #include "definitions.h" -#include "operation.h" #include "storage.h" #include #include @@ -43,7 +42,7 @@ class Cache : public Storage * cache level to true, and the victim line is chosen/written back. * @param the address that must be present in cache. */ - void fetch_resource(Operation op, int address); + void fetch_resource(int address); /** * An array of metadata about elements in `data`. * If the first value of an element is negative, the corresponding diff --git a/inc/operation.h b/inc/operation.h deleted file mode 100644 index a35344e..0000000 --- a/inc/operation.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef OPERATION_H -#define OPERATION_H - -enum Operation { - READ, - WRITE -}; - -#endif /* OPERATION_H_INCLUDED */ \ No newline at end of file diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 1224aa9..5e071ac 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -34,7 +34,7 @@ Response Cache::write(Accessor accessor, signed int data, int address) this->requester = accessor; if (this->requester == accessor) { - fetch_resource(WRITE,address); + fetch_resource(address); if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { @@ -49,7 +49,8 @@ Response Cache::write(Accessor accessor, signed int data, int address) return r; } -Response Cache::write_line(Accessor accessor, std::array data_line, int address) +Response Cache::write_line( + Accessor accessor, std::array data_line, int address) { Response r = WAIT; @@ -58,7 +59,7 @@ Response Cache::write_line(Accessor accessor, std::array this->requester = accessor; if (this->requester == accessor) { - fetch_resource(WRITE,address); + fetch_resource(address); if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { @@ -74,13 +75,16 @@ Response Cache::write_line(Accessor accessor, std::array } // TODO: tests for multi level cache -Response Cache::read(Accessor accessor, int address, std::array &data_line) +Response Cache::read( + Accessor accessor, + int address, + std::array &data_line) { Response r = WAIT; if (this->requester == IDLE) this->requester = accessor; if (this->requester == accessor) { - fetch_resource(READ,address); + fetch_resource(address); if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { @@ -99,7 +103,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data) if (this->requester == IDLE) this->requester = accessor; if (this->requester == accessor) { - fetch_resource(READ,address); + fetch_resource(address); if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { @@ -112,7 +116,7 @@ Response Cache::read_word(Accessor accessor, int address, signed int &data) return r; } -void Cache::fetch_resource(Operation op, int expected) +void Cache::fetch_resource(int expected) { Response r = OK; int tag, index, offset; @@ -128,12 +132,12 @@ void Cache::fetch_resource(Operation op, int expected) if (meta->at(1) >= 0) { // occupant is dirty // writing line to DRam in case of dirty cache eviction - r = this->lower->write_line(L1CACHE, actual, ((index << LINE_SPEC) + (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC)))); + r = this->lower->write_line( + L1CACHE, actual, + ((index << LINE_SPEC) + + (meta->at(0) << (L1_CACHE_SPEC + LINE_SPEC)))); if (r == OK) { meta->at(1) = -1; - if(op == READ){ - r = WAIT; //if operation is read, need to wait until cache is loaded with right value from memory address, if operation is write, then this is not necessary - } } } else { r = this->lower->read(L1CACHE, expected, actual); -- cgit v1.2.3 From d534555fbb9562a819d34ea874a711d737d051ae Mon Sep 17 00:00:00 2001 From: bd Date: Tue, 11 Mar 2025 16:39:47 -0400 Subject: Rename read/write to read_line and write_word --- inc/cache.h | 13 +++-- inc/dram.h | 18 ++++--- inc/storage.h | 4 +- src/cli/cli.cc | 2 +- src/storage/cache.cc | 6 +-- src/storage/dram.cc | 22 +++++---- tests/cache.cc | 38 +++++++-------- tests/dram.cc | 132 +++++++++++++++++++++++++-------------------------- 8 files changed, 125 insertions(+), 110 deletions(-) (limited to 'src') diff --git a/inc/cache.h b/inc/cache.h index 20a40c2..17abcdd 100644 --- a/inc/cache.h +++ b/inc/cache.h @@ -20,13 +20,18 @@ class Cache : public Storage Cache(Storage *lower, int delay); ~Cache(); - Response write(Accessor accessor, signed int data, int address) override; - Response write_line(Accessor accessor, std::array data_line, int address) override; - Response read( + Response + write_word(Accessor accessor, signed int data, int address) override; + Response write_line( + Accessor accessor, + std::array data_line, + int address) override; + Response read_line( Accessor accessor, int address, std::array &data_line) override; - Response read_word(Accessor accessor, int address, signed int &data) override; + Response + read_word(Accessor accessor, int address, signed int &data) override; /** * Getter for the meta attribute. diff --git a/inc/dram.h b/inc/dram.h index 7774040..2771c3e 100644 --- a/inc/dram.h +++ b/inc/dram.h @@ -17,15 +17,20 @@ class Dram : public Storage Dram(int lines, int delay); ~Dram(); - Response write(Accessor accessor, signed int data, int address) override; - Response read( + Response + write_word(Accessor accessor, signed int data, int address) override; + Response read_line( Accessor accessor, int address, std::array &data_line) override; - Response write_line(Accessor accessor, std::array data_line, int address) override; - Response read_word(Accessor accessor, int address, signed int &data) override; + Response write_line( + Accessor accessor, + std::array data_line, + int address) override; + Response + read_word(Accessor accessor, int address, signed int &data) override; - private: + private: /** * Helper for `write` a word */ @@ -33,7 +38,8 @@ class Dram : public Storage /** * Helper for writing a line. */ - void do_write_line(std::array data_line, int address); + void + do_write_line(std::array data_line, int address); /** * Helper for `read` a line */ diff --git a/inc/storage.h b/inc/storage.h index fc93d7a..b54a6f7 100644 --- a/inc/storage.h +++ b/inc/storage.h @@ -20,7 +20,7 @@ class Storage * @param the address to write to. * @return a status code reflecting the state of the request. */ - virtual Response write(Accessor accessor, signed int data, int address) = 0; + virtual Response write_word(Accessor accessor, signed int data, int address) = 0; /** * Write a data line to given address in this level of storage @@ -35,7 +35,7 @@ class Storage * @return a status code reflecting the state of the request, and the * data being returned. */ - virtual Response read( + virtual Response read_line( Accessor accessor, int address, std::array &data) = 0; diff --git a/src/cli/cli.cc b/src/cli/cli.cc index 0729e00..a885aee 100644 --- a/src/cli/cli.cc +++ b/src/cli/cli.cc @@ -115,7 +115,7 @@ void Cli::load(Accessor accessor, int address) void Cli::store(Accessor accessor, int data, int address) { - Response r = this->cache->write(accessor, data, address); + Response r = this->cache->write_word(accessor, data, address); std::cout << r << " to " << accessor << " storing " << data << " in" << address << std::endl; } diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 5e071ac..533d0ec 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -25,7 +25,7 @@ Cache::~Cache() delete this->data; } -Response Cache::write(Accessor accessor, signed int data, int address) +Response Cache::write_word(Accessor accessor, signed int data, int address) { Response r = WAIT; @@ -75,7 +75,7 @@ Response Cache::write_line( } // TODO: tests for multi level cache -Response Cache::read( +Response Cache::read_line( Accessor accessor, int address, std::array &data_line) @@ -140,7 +140,7 @@ void Cache::fetch_resource(int expected) meta->at(1) = -1; } } else { - r = this->lower->read(L1CACHE, expected, actual); + r = this->lower->read_line(L1CACHE, expected, actual); if (r == OK) { meta->at(0) = tag; } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 76c4f90..f375a76 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -28,7 +28,9 @@ void Dram::do_write(signed int data, int address) this->data->at(line).at(word) = data; } -void Dram::do_write_line(std::array data_line, int address){ +void Dram::do_write_line( + std::array data_line, int address) +{ int line = address / LINE_SIZE; this->data->at(line) = data_line; } @@ -46,9 +48,8 @@ void Dram::do_read_word(signed int &data, int address) data = this->data->at(line).at(word); } - - -Response Dram::write_line(Accessor accessor, std::array data_line, int address) +Response Dram::write_line( + Accessor accessor, std::array data_line, int address) { Response r = WAIT; @@ -70,8 +71,7 @@ Response Dram::write_line(Accessor accessor, std::array d return r; } - -Response Dram::write(Accessor accessor, signed int data, int address) +Response Dram::write_word(Accessor accessor, signed int data, int address) { Response r = WAIT; @@ -94,7 +94,11 @@ Response Dram::write(Accessor accessor, signed int data, int address) return r; } -Response Dram::read(Accessor accessor, int address, std::array& data_line) { +Response Dram::read_line( + Accessor accessor, + int address, + std::array &data_line) +{ Response r = WAIT; if (this->requester == IDLE) @@ -110,7 +114,8 @@ Response Dram::read(Accessor accessor, int address, std::arrayrequester == IDLE) @@ -149,4 +154,3 @@ std::ostream &operator<<(std::ostream &os, const Dram &d) std::cout.fill(default_fill); return os; } - diff --git a/tests/cache.cc b/tests/cache.cc index e8a257f..d7b3444 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -25,7 +25,7 @@ TEST_CASE("no delay stores instantly", "[cache]") Response r; - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == OK); c->resolve(); @@ -54,7 +54,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]") int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == WAIT); // WAIT actual = c->view(0, 1)[0]; @@ -62,7 +62,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]") c->resolve(); } - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == OK); actual = d->view(0, 1)[0]; @@ -90,7 +90,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]") int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == BLOCKED); // BLOCKED actual = c->view(0, 1)[0]; @@ -98,7 +98,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]") c->resolve(); } - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == OK); actual = d->view(0, 1)[0]; @@ -126,7 +126,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]") int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == BLOCKED); // BLOCKED actual = c->view(0, 1)[0]; @@ -135,7 +135,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]") } for (i = 0; i < delay; ++i) { - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == WAIT); // WAIT actual = c->view(0, 1)[0]; @@ -143,7 +143,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]") c->resolve(); } - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == OK); c->resolve(); @@ -173,10 +173,10 @@ TEST_CASE( int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == BLOCKED); // BLOCKED - r = c->write(FETCH, w, 0b1); + r = c->write_word(FETCH, w, 0b1); CHECK(r == WAIT); // WAIT actual = c->view(0, 1)[0]; @@ -184,9 +184,9 @@ TEST_CASE( c->resolve(); } - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == OK); - r = c->write(FETCH, w, 0b1); + r = c->write_word(FETCH, w, 0b1); CHECK(r == WAIT); c->resolve(); @@ -199,7 +199,7 @@ TEST_CASE( actual = c->view(0, 1)[0]; REQUIRE(expected == actual); - r = c->write(FETCH, w, 0b1); + r = c->write_word(FETCH, w, 0b1); // this should have been loaded already! CHECK(r == OK); @@ -228,10 +228,10 @@ TEST_CASE( int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == BLOCKED); // BLOCKED - r = c->write(FETCH, w, 0b100); + r = c->write_word(FETCH, w, 0b100); CHECK(r == WAIT); // WAIT actual = c->view(0, 1)[0]; @@ -239,9 +239,9 @@ TEST_CASE( c->resolve(); } - r = c->write(MEM, w, 0b0); + r = c->write_word(MEM, w, 0b0); CHECK(r == OK); - r = c->write(FETCH, w, 0b1); + r = c->write_word(FETCH, w, 0b1); CHECK(r == WAIT); c->resolve(); @@ -255,7 +255,7 @@ TEST_CASE( REQUIRE(expected == actual); for (i = 0; i < delay + 2; ++i) { - r = c->write(FETCH, w, 0b100); + r = c->write_word(FETCH, w, 0b100); CHECK(r == BLOCKED); // BLOCKED actual = c->view(0, 1)[0]; @@ -263,7 +263,7 @@ TEST_CASE( c->resolve(); } - r = c->write(FETCH, w, 0b1); + r = c->write_word(FETCH, w, 0b1); CHECK(r == OK); c->resolve(); diff --git a/tests/dram.cc b/tests/dram.cc index 8425d3b..72a6d14 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -22,7 +22,7 @@ TEST_CASE( signed int w = 0x11223344; - Response r = d->write(MEM, w, 0x00000000); + Response r = d->write_word(MEM, w, 0x00000000); CHECK(r == OK); expected.at(0) = w; @@ -46,7 +46,7 @@ TEST_CASE( int i; Response r; for (i = 0; i < delay; ++i) { - r = d->write(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x00000000); CHECK(r == WAIT); actual = d->view(0, 1)[0]; @@ -54,7 +54,7 @@ TEST_CASE( d->resolve(); } - r = d->write(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x00000000); CHECK(r == OK); d->resolve(); @@ -81,7 +81,7 @@ TEST_CASE( int i; Response r; for (i = 0; i < delay; ++i) { - r = d->write(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x00000000); CHECK(r == WAIT); actual = d->view(0, 1)[0]; @@ -89,11 +89,11 @@ TEST_CASE( d->resolve(); } - r = d->write(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x00000000); REQUIRE(r == OK); // clock cycle did NOT resolve yet! // this fetch should not make progress - r = d->write(FETCH, w, 0x00000001); + r = d->write_word(FETCH, w, 0x00000001); CHECK(r == WAIT); actual = d->view(0, 1)[0]; @@ -105,7 +105,7 @@ TEST_CASE( REQUIRE(expected == actual); for (i = 0; i < delay; ++i) { - r = d->write(FETCH, w, 0x00000001); + r = d->write_word(FETCH, w, 0x00000001); CHECK(r == WAIT); actual = d->view(0, 1)[0]; @@ -113,7 +113,7 @@ TEST_CASE( d->resolve(); } - r = d->write(FETCH, w, 0x00000001); + r = d->write_word(FETCH, w, 0x00000001); actual = d->view(0, 1)[0]; CHECK(r == OK); @@ -140,10 +140,10 @@ TEST_CASE( int i; Response r; for (i = 0; i < delay; ++i) { - r = d->write(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x00000000); CHECK(r == WAIT); - r = d->write(FETCH, w, 0x00000001); + r = d->write_word(FETCH, w, 0x00000001); CHECK(r == WAIT); actual = d->view(0, 1)[0]; @@ -151,9 +151,9 @@ TEST_CASE( d->resolve(); } - r = d->write(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x00000000); CHECK(r == OK); - r = d->write(FETCH, w, 0x00000001); + r = d->write_word(FETCH, w, 0x00000001); CHECK(r == WAIT); d->resolve(); @@ -162,10 +162,10 @@ TEST_CASE( REQUIRE(expected == actual); for (i = 0; i < delay; ++i) { - r = d->write(FETCH, w, 0x00000001); + r = d->write_word(FETCH, w, 0x00000001); CHECK(r == WAIT); - r = d->write(MEM, w, 0x00000003); + r = d->write_word(MEM, w, 0x00000003); CHECK(r == WAIT); actual = d->view(0, 1)[0]; @@ -173,10 +173,10 @@ TEST_CASE( d->resolve(); } - r = d->write(FETCH, w, 0x00000001); + r = d->write_word(FETCH, w, 0x00000001); actual = d->view(0, 1)[0]; CHECK(r == OK); - r = d->write(MEM, w, 0x00000003); + r = d->write_word(MEM, w, 0x00000003); CHECK(r == WAIT); expected.at(1) = w; @@ -378,19 +378,19 @@ TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, rea int addr = 0x00000000; d->write_line(MEM, expected, addr); - Response r = d->read(MEM, 0x00000000, actual); + Response r = d->read_line(MEM, 0x00000000, actual); CHECK(r == OK); REQUIRE(expected == actual); - r = d->read(MEM, 0x00000001, actual); + r = d->read_line(MEM, 0x00000001, actual); CHECK(r == OK); REQUIRE(expected == actual); - r = d->read(MEM, 0x00000002, actual); + r = d->read_line(MEM, 0x00000002, actual); CHECK(r == OK); REQUIRE(expected == actual); - r = d->read(MEM, 0x00000003, actual); + r = d->read_line(MEM, 0x00000003, actual); CHECK(r == OK); REQUIRE(expected == actual); @@ -420,13 +420,13 @@ TEST_CASE("Construct singleton dram, write a line to an address in three cycles, d->resolve(); for (i = 0; i < delay; ++i) { - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); CHECK(r == OK); d->resolve(); REQUIRE(expected == actual); @@ -456,30 +456,30 @@ TEST_CASE( d->resolve(); for (i = 0; i < delay; ++i) { - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); REQUIRE(r == OK); - r = d->read(FETCH, 0x00000003, actual); + r = d->read_line(FETCH, 0x00000003, actual); CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); actual = {0,0,0,0}; for (i = 0; i < delay; ++i) { - r = d->read(FETCH, 0x00000000, actual); + r = d->read_line(FETCH, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(FETCH, 0x00000000, actual); + r = d->read_line(FETCH, 0x00000000, actual); REQUIRE(r == OK); - r = d->read(MEM, 0x00000002, actual); + r = d->read_line(MEM, 0x00000002, actual); CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); @@ -512,36 +512,36 @@ TEST_CASE( for (i = 0; i < delay; ++i) { - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); - r = d->read(FETCH, 0x00000002, actual); + r = d->read_line(FETCH, 0x00000002, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); REQUIRE(r == OK); - r = d->read(FETCH, 0x00000003, actual); + r = d->read_line(FETCH, 0x00000003, actual); CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); actual = {0,0,0,0}; for (i = 0; i < delay; ++i) { - r = d->read(FETCH, 0x00000000, actual); + r = d->read_line(FETCH, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); - r = d->read(MEM, 0x00000002, actual); + r = d->read_line(MEM, 0x00000002, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(FETCH, 0x00000000, actual); + r = d->read_line(FETCH, 0x00000000, actual); REQUIRE(r == OK); - r = d->read(MEM, 0x00000002, actual); + r = d->read_line(MEM, 0x00000002, actual); CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); @@ -561,24 +561,24 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a signed int w = 0x11223311; int addr = 0x00000000; for(int i=0; iwrite(MEM, w, addr++); + Response r = d->write_word(MEM, w, addr++); CHECK(r == OK); expected.at(i) = w++; } - Response r = d->read(MEM, 0x00000000, actual); + Response r = d->read_line(MEM, 0x00000000, actual); CHECK(r == OK); REQUIRE(expected == actual); - r = d->read(MEM, 0x00000001, actual); + r = d->read_line(MEM, 0x00000001, actual); CHECK(r == OK); REQUIRE(expected == actual); - r = d->read(MEM, 0x00000002, actual); + r = d->read_line(MEM, 0x00000002, actual); CHECK(r == OK); REQUIRE(expected == actual); - r = d->read(MEM, 0x00000003, actual); + r = d->read_line(MEM, 0x00000003, actual); CHECK(r == OK); REQUIRE(expected == actual); @@ -599,22 +599,22 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a Response r; for(i=0; iwrite(MEM, w, addr); + r = d->write_word(MEM, w, addr); d->resolve(); } - r = d->write(MEM, w, addr++); + r = d->write_word(MEM, w, addr++); d->resolve(); expected.at(i) = w++; } for (i = 0; i < delay; ++i) { - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); CHECK(r == OK); d->resolve(); REQUIRE(expected == actual); @@ -636,39 +636,39 @@ TEST_CASE( Response r; for(i=0; iwrite(MEM, w, addr); + r = d->write_word(MEM, w, addr); d->resolve(); } - r = d->write(MEM, w, addr++); + r = d->write_word(MEM, w, addr++); d->resolve(); expected.at(i) = w++; } for (i = 0; i < delay; ++i) { - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); REQUIRE(r == OK); - r = d->read(FETCH, 0x00000003, actual); + r = d->read_line(FETCH, 0x00000003, actual); CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); actual = {0,0,0,0}; for (i = 0; i < delay; ++i) { - r = d->read(FETCH, 0x00000000, actual); + r = d->read_line(FETCH, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(FETCH, 0x00000000, actual); + r = d->read_line(FETCH, 0x00000000, actual); REQUIRE(r == OK); - r = d->read(MEM, 0x00000002, actual); + r = d->read_line(MEM, 0x00000002, actual); CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); @@ -692,45 +692,45 @@ TEST_CASE( Response r; for(i=0; iwrite(MEM, w, addr); + r = d->write_word(MEM, w, addr); d->resolve(); } - r = d->write(MEM, w, addr++); + r = d->write_word(MEM, w, addr++); d->resolve(); expected.at(i) = w++; } for (i = 0; i < delay; ++i) { - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); - r = d->read(FETCH, 0x00000002, actual); + r = d->read_line(FETCH, 0x00000002, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(MEM, 0x00000000, actual); + r = d->read_line(MEM, 0x00000000, actual); REQUIRE(r == OK); - r = d->read(FETCH, 0x00000003, actual); + r = d->read_line(FETCH, 0x00000003, actual); CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); actual = {0,0,0,0}; for (i = 0; i < delay; ++i) { - r = d->read(FETCH, 0x00000000, actual); + r = d->read_line(FETCH, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); - r = d->read(MEM, 0x00000002, actual); + r = d->read_line(MEM, 0x00000002, actual); CHECK(r == WAIT); REQUIRE(expected != actual); d->resolve(); } - r = d->read(FETCH, 0x00000000, actual); + r = d->read_line(FETCH, 0x00000000, actual); REQUIRE(r == OK); - r = d->read(MEM, 0x00000002, actual); + r = d->read_line(MEM, 0x00000002, actual); CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); @@ -753,7 +753,7 @@ TEST_CASE("Sidedoor bypasses delay", "[dram]") int i; Response r; for (i = 0; i < delay - 1; ++i) { - r = d->write(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x00000000); CHECK(r == WAIT); actual = d->view(0, 1)[0]; @@ -761,12 +761,12 @@ TEST_CASE("Sidedoor bypasses delay", "[dram]") d->resolve(); } - r = d->write(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x00000000); CHECK(r == WAIT); actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - r = d->write(SIDE, w, 0x00000001); + r = d->write_word(SIDE, w, 0x00000001); actual = d->view(0, 1)[0]; CHECK(r == OK); -- cgit v1.2.3