From db0acc382a40a44a7d3859bd8ecf822dea86f622 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 20:56:00 -0400 Subject: cache store single test --- tests/cache.cc | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) (limited to 'tests/cache.cc') diff --git a/tests/cache.cc b/tests/cache.cc index 3c1fba6..55592ae 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -1,12 +1,43 @@ #include "cache.h" #include "definitions.h" +#include "dram.h" #include -TEST_CASE("Constructor singleton dram", "[cache]") +TEST_CASE("Constructor singleton cache", "[cache]") { - Cache *c = new Cache(1, nullptr, LINE_SIZE); + Cache *c = new Cache(nullptr, 0); std::array expected = {0, 0, 0, 0}; std::array actual = c->view(0, 1)[0]; REQUIRE(expected == actual); delete c; } + +// TEST_CASE("no delay stores instantly", "[cache]") +// { +// int delay = 0; +// Dram *d = new Dram(MEM_SIZE, delay); +// Cache *c = new Cache(d, delay); +// std::array expected = {0, 0, 0, 0}; +// std::array actual = d->view(0, 1)[0]; +// CHECK(expected == actual); + +// signed int w = 0x11223344; + +// Response r; + +// r = c->write(MEM, w, 0x0000000000000); +// CHECK(r == OK); +// d->resolve(); +// c->resolve(); + +// expected.at(0) = w; +// actual = c->view(0, 1)[0]; +// REQUIRE(expected == actual); + +// actual = d->view(0, 1)[0]; +// // we do NOT write back now! +// REQUIRE(expected != actual); + +// delete d; +// delete c; +// } -- cgit v1.2.3 From 05ce888aa6dd2fba5e295c15497cb80bbc21c9f1 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 21:39:07 -0400 Subject: Cache object issues with uninitialized fields, another cache test --- src/storage/cache.cc | 19 +++++++++------- tests/cache.cc | 63 +++++++++++++++++++++++++++++++++++++++++++--------- tests/dram.cc | 2 -- 3 files changed, 64 insertions(+), 20 deletions(-) (limited to 'tests/cache.cc') diff --git a/src/storage/cache.cc b/src/storage/cache.cc index f1ae238..52f13b9 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -8,9 +8,12 @@ Cache::Cache(Storage *lower, int delay) { this->data = new std::vector>; this->data->resize(L1_CACHE_SIZE); - this->lower = lower; this->delay = delay; - this->meta.fill({-1}); + this->is_waiting = false; + this->lower = lower; + this->meta.fill({-1, -1}); + this->requester = IDLE; + this->wait_time = this->delay; } Cache::~Cache() { delete this->data; } @@ -25,13 +28,12 @@ Response Cache::write(Accessor accessor, signed int data, int address) if (this->requester == accessor) { fetch_resource(address); - if (this->is_waiting == true) + if (this->is_waiting) r = BLOCKED; else if (this->wait_time == 0) { int tag, index, offset; get_bit_fields(address, &tag, &index, &offset); this->data->at(index).at(offset) = data; - r = OK; } } @@ -48,16 +50,16 @@ Response Cache::read( void Cache::fetch_resource(int expected) { Response r = OK; - int etag, index, eoffset, atag; + int tag, index, offset; std::array actual; std::array meta; - get_bit_fields(expected, &etag, &index, &eoffset); + get_bit_fields(expected, &tag, &index, &offset); meta = this->meta.at(index); - if (atag != etag) { + if (this->meta[index][0] != tag) { // address not in cache - if (this->meta[index][0] >= 0) { + if (this->meta[index][1] >= 0) { // occupant is dirty // TODO r = WAIT; @@ -65,6 +67,7 @@ void Cache::fetch_resource(int expected) actual = this->data->at(index); r = this->lower->read(L1CACHE, expected, actual); // clear dirty bit and set tag? + } } diff --git a/tests/cache.cc b/tests/cache.cc index 55592ae..9e6521a 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -12,31 +12,74 @@ TEST_CASE("Constructor singleton cache", "[cache]") delete c; } -// TEST_CASE("no delay stores instantly", "[cache]") +TEST_CASE("no delay stores instantly", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + Response r; + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + d->resolve(); + c->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +// TEST_CASE("cache takes \"forever\"", "[cache]") // { // int delay = 0; // Dram *d = new Dram(MEM_SIZE, delay); -// Cache *c = new Cache(d, delay); +// Cache *c = new Cache(d, delay + 2); // std::array expected = {0, 0, 0, 0}; // std::array actual = d->view(0, 1)[0]; // CHECK(expected == actual); // signed int w = 0x11223344; +// int i; // Response r; - -// r = c->write(MEM, w, 0x0000000000000); +// for (i = 0; i < delay + 2; ++i) { +// r = c->write(MEM, w, 0x0000000000000); +// CHECK(r == WAIT); + +// // keep dram busy +// r = d->write(MEM, w, 0x0000000000101); +// CHECK(r == OK); + +// actual = c->view(0, 1)[0]; +// REQUIRE(expected == actual); +// c->resolve(); +// d->resolve(); +// } + +// r = c->write(MEM, w, 0x0000000000000); // CHECK(r == OK); // d->resolve(); -// c->resolve(); - -// expected.at(0) = w; -// actual = c->view(0, 1)[0]; -// REQUIRE(expected == actual); // actual = d->view(0, 1)[0]; // // we do NOT write back now! -// REQUIRE(expected != actual); +// REQUIRE(expected == actual); + +// expected.at(1) = w; +// actual = c->view(0, 1)[0]; +// REQUIRE(expected == actual); // delete d; // delete c; diff --git a/tests/dram.cc b/tests/dram.cc index 95ef90a..27fc24f 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -85,8 +85,6 @@ TEST_CASE( CHECK(r == WAIT); actual = d->view(0, 1)[0]; - CHECK(r == WAIT); - REQUIRE(expected == actual); d->resolve(); } -- cgit v1.2.3 From 7506edbc6b8c761c3e810f09fd88c1dc7ab3e717 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 23:49:29 -0400 Subject: Properly set cache metadata when a value is loaded --- src/storage/cache.cc | 15 +++-- src/storage/dram.cc | 3 + tests/cache.cc | 169 ++++++++++++++++++++++++++++++++++++++------------- 3 files changed, 139 insertions(+), 48 deletions(-) (limited to 'tests/cache.cc') diff --git a/src/storage/cache.cc b/src/storage/cache.cc index 52f13b9..2031367 100644 --- a/src/storage/cache.cc +++ b/src/storage/cache.cc @@ -34,6 +34,7 @@ Response Cache::write(Accessor accessor, signed int data, int address) int tag, index, offset; get_bit_fields(address, &tag, &index, &offset); this->data->at(index).at(offset) = data; + this->meta[index].at(1) = 1; r = OK; } } @@ -52,22 +53,24 @@ void Cache::fetch_resource(int expected) Response r = OK; int tag, index, offset; std::array actual; - std::array meta; + std::array *meta; get_bit_fields(expected, &tag, &index, &offset); - meta = this->meta.at(index); + meta = &this->meta.at(index); - if (this->meta[index][0] != tag) { + if (meta->at(0) != tag) { // address not in cache - if (this->meta[index][1] >= 0) { + if (meta->at(1) >= 0) { // occupant is dirty // TODO r = WAIT; } else { actual = this->data->at(index); r = this->lower->read(L1CACHE, expected, actual); - // clear dirty bit and set tag? - + if (r == OK) { + meta->at(0) = tag; + meta->at(1) = -1; + } } } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 9dab4ed..441f10b 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -57,13 +57,16 @@ Response Dram::read( Accessor accessor, int address, std::array &data) { Response r = WAIT; + if (this->requester == IDLE) this->requester = accessor; + if (this->requester == accessor) { if (this->wait_time == 0) { this->do_read(data, address); r = OK; } } + return r; } diff --git a/tests/cache.cc b/tests/cache.cc index 9e6521a..64819b6 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -42,45 +42,130 @@ TEST_CASE("no delay stores instantly", "[cache]") delete c; } -// TEST_CASE("cache takes \"forever\"", "[cache]") -// { -// int delay = 0; -// Dram *d = new Dram(MEM_SIZE, delay); -// Cache *c = new Cache(d, delay + 2); -// std::array expected = {0, 0, 0, 0}; -// std::array actual = d->view(0, 1)[0]; -// CHECK(expected == actual); - -// signed int w = 0x11223344; - -// int i; -// Response r; -// for (i = 0; i < delay + 2; ++i) { -// r = c->write(MEM, w, 0x0000000000000); -// CHECK(r == WAIT); - -// // keep dram busy -// r = d->write(MEM, w, 0x0000000000101); -// CHECK(r == OK); - -// actual = c->view(0, 1)[0]; -// REQUIRE(expected == actual); -// c->resolve(); -// d->resolve(); -// } - -// r = c->write(MEM, w, 0x0000000000000); -// CHECK(r == OK); -// d->resolve(); - -// actual = d->view(0, 1)[0]; -// // we do NOT write back now! -// REQUIRE(expected == actual); - -// expected.at(1) = w; -// actual = c->view(0, 1)[0]; -// REQUIRE(expected == actual); - -// delete d; -// delete c; -// } +TEST_CASE("cache takes \"forever\"", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay); + Cache *c = new Cache(d, delay + 2); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == WAIT); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +TEST_CASE("dram takes \"forever\"", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay + 2); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == BLOCKED); // BLOCKED + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +TEST_CASE("dram and cache take \"forever\"", "[cache]") +{ + int delay = 2; + Dram *d = new Dram(MEM_SIZE, delay + 2); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == BLOCKED); // BLOCKED + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + for (i = 0; i < delay; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == WAIT); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + c->resolve(); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} -- cgit v1.2.3 From 368e27a90e1b78543dd6461ba640a7942f0f2250 Mon Sep 17 00:00:00 2001 From: bd Date: Sun, 9 Mar 2025 23:57:37 -0400 Subject: More cache store tests --- tests/cache.cc | 128 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) (limited to 'tests/cache.cc') diff --git a/tests/cache.cc b/tests/cache.cc index 64819b6..ee26d68 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -169,3 +169,131 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]") delete d; delete c; } + +TEST_CASE("dram takes \"forever\", two concurrent requests same index", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay + 2); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == BLOCKED); // BLOCKED + + r = c->write(FETCH, w, 0x0000000000001); + CHECK(r == WAIT); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + r = c->write(FETCH, w, 0x0000000000001); + CHECK(r == WAIT); + + c->resolve(); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + r = c->write(FETCH, w, 0x0000000000001); + // this should have been loaded already! + CHECK(r == OK); + + c->resolve(); + d->resolve(); + + expected.at(1) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +TEST_CASE("dram takes \"forever\", two concurrent requests different index", "[cache]") +{ + int delay = 0; + Dram *d = new Dram(MEM_SIZE, delay + 2); + Cache *c = new Cache(d, delay); + std::array expected = {0, 0, 0, 0}; + std::array actual = d->view(0, 1)[0]; + CHECK(expected == actual); + + signed int w = 0x11223344; + + int i; + Response r; + for (i = 0; i < delay + 2; ++i) { + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == BLOCKED); // BLOCKED + + r = c->write(FETCH, w, 0x0000000000100); + CHECK(r == WAIT); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(MEM, w, 0x0000000000000); + CHECK(r == OK); + r = c->write(FETCH, w, 0x0000000000001); + CHECK(r == WAIT); + + c->resolve(); + d->resolve(); + + actual = d->view(0, 1)[0]; + // we do NOT write back now! + REQUIRE(expected == actual); + + expected.at(0) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + for (i = 0; i < delay + 2; ++i) { + r = c->write(FETCH, w, 0x0000000000100); + CHECK(r == BLOCKED); // WAIT + + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + c->resolve(); + d->resolve(); + } + + r = c->write(FETCH, w, 0x0000000000001); + CHECK(r == OK); + + c->resolve(); + d->resolve(); + + expected.at(1) = w; + actual = c->view(0, 1)[0]; + REQUIRE(expected == actual); + + delete d; + delete c; +} + +TEST_CASE("dram takes \"forever\", two concurrent requests different tag", "[cache]") +{ + // TODO +} -- cgit v1.2.3 From d0ec568e4f063fd1c85087582283f3511e0a12ec Mon Sep 17 00:00:00 2001 From: bd Date: Mon, 10 Mar 2025 00:04:09 -0400 Subject: Specify memory addresses in cache tests in binary as intended --- tests/cache.cc | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'tests/cache.cc') diff --git a/tests/cache.cc b/tests/cache.cc index ee26d68..8d1e806 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -25,7 +25,7 @@ TEST_CASE("no delay stores instantly", "[cache]") Response r; - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == OK); d->resolve(); c->resolve(); @@ -56,7 +56,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]") int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == WAIT); // WAIT actual = c->view(0, 1)[0]; @@ -65,7 +65,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]") d->resolve(); } - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == OK); d->resolve(); @@ -95,7 +95,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]") int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == BLOCKED); // BLOCKED actual = c->view(0, 1)[0]; @@ -104,7 +104,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]") d->resolve(); } - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == OK); d->resolve(); @@ -134,7 +134,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]") int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == BLOCKED); // BLOCKED actual = c->view(0, 1)[0]; @@ -144,7 +144,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]") } for (i = 0; i < delay; ++i) { - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == WAIT); // WAIT actual = c->view(0, 1)[0]; @@ -153,7 +153,7 @@ TEST_CASE("dram and cache take \"forever\"", "[cache]") d->resolve(); } - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == OK); c->resolve(); d->resolve(); @@ -184,10 +184,10 @@ TEST_CASE("dram takes \"forever\", two concurrent requests same index", "[cache] int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == BLOCKED); // BLOCKED - r = c->write(FETCH, w, 0x0000000000001); + r = c->write(FETCH, w, 0b1); CHECK(r == WAIT); // WAIT actual = c->view(0, 1)[0]; @@ -196,9 +196,9 @@ TEST_CASE("dram takes \"forever\", two concurrent requests same index", "[cache] d->resolve(); } - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == OK); - r = c->write(FETCH, w, 0x0000000000001); + r = c->write(FETCH, w, 0b1); CHECK(r == WAIT); c->resolve(); @@ -212,7 +212,7 @@ TEST_CASE("dram takes \"forever\", two concurrent requests same index", "[cache] actual = c->view(0, 1)[0]; REQUIRE(expected == actual); - r = c->write(FETCH, w, 0x0000000000001); + r = c->write(FETCH, w, 0b1); // this should have been loaded already! CHECK(r == OK); @@ -241,10 +241,10 @@ TEST_CASE("dram takes \"forever\", two concurrent requests different index", "[c int i; Response r; for (i = 0; i < delay + 2; ++i) { - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == BLOCKED); // BLOCKED - r = c->write(FETCH, w, 0x0000000000100); + r = c->write(FETCH, w, 0b100); CHECK(r == WAIT); // WAIT actual = c->view(0, 1)[0]; @@ -253,9 +253,9 @@ TEST_CASE("dram takes \"forever\", two concurrent requests different index", "[c d->resolve(); } - r = c->write(MEM, w, 0x0000000000000); + r = c->write(MEM, w, 0b0); CHECK(r == OK); - r = c->write(FETCH, w, 0x0000000000001); + r = c->write(FETCH, w, 0b1); CHECK(r == WAIT); c->resolve(); @@ -270,8 +270,8 @@ TEST_CASE("dram takes \"forever\", two concurrent requests different index", "[c REQUIRE(expected == actual); for (i = 0; i < delay + 2; ++i) { - r = c->write(FETCH, w, 0x0000000000100); - CHECK(r == BLOCKED); // WAIT + r = c->write(FETCH, w, 0b100); + CHECK(r == BLOCKED); // BLOCKED actual = c->view(0, 1)[0]; REQUIRE(expected == actual); @@ -279,7 +279,7 @@ TEST_CASE("dram takes \"forever\", two concurrent requests different index", "[c d->resolve(); } - r = c->write(FETCH, w, 0x0000000000001); + r = c->write(FETCH, w, 0b1); CHECK(r == OK); c->resolve(); -- cgit v1.2.3