From 23d3ebb2702e6b08c7f6b997067e1bc76483b813 Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 16 Apr 2025 22:22:09 -0400 Subject: Partial fixes for changes in DRAM/Cache, including uncovered bug --- tests/controller.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/controller.cc') diff --git a/tests/controller.cc b/tests/controller.cc index a009a70..74284b7 100644 --- a/tests/controller.cc +++ b/tests/controller.cc @@ -16,7 +16,7 @@ class ControllerPipeFixture ControllerPipeFixture() { this->d = new Dram(1); - this->c = new Cache(this->d, 0); + this->c = new Cache(this->d, 5, 0, 0); IF *f = new IF(nullptr); ID *d = new ID(f); -- cgit v1.2.3 From 796b2691146a3a4eaace4fa155d3c0c2f7379832 Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 16 Apr 2025 23:35:59 -0400 Subject: Fix a bug related to parsing immediates in decode --- inc/pipe_spec.h | 17 +++++++++++++++++ src/sim/id.cc | 13 +++++++------ tests/controller.cc | 2 +- tests/id.cc | 2 +- 4 files changed, 26 insertions(+), 8 deletions(-) (limited to 'tests/controller.cc') diff --git a/inc/pipe_spec.h b/inc/pipe_spec.h index 772314e..d211b72 100644 --- a/inc/pipe_spec.h +++ b/inc/pipe_spec.h @@ -65,4 +65,21 @@ */ #define GET_MID_BITS(k, m, n) GET_LS_BITS((k) >> (m), ((n) - (m))) +/** + * Return the bits from integer K starting at N and ending at M using a bit + * mask, but sign-extends the result. This is required to parse immediates. + * @param the integer to be parsed + * @param the index of the starting bit to be parsed + * @param the index of the ending bit to be parsed + * @return a section of bits from K + */ +// clang-format off +#define GET_BITS_SIGN_EXTEND(k, m, n) \ + ({\ + int _f = GET_MID_BITS(k, m, n); \ + int _w = (n) - (m) - (1); \ + _f = (_f & (1 << (_w - 1))) ? (_f | (-1 << _w)) : _f; \ + }) +// clang-format on + #endif /* DEFINITIONS_H_INCLUDED */ diff --git a/src/sim/id.cc b/src/sim/id.cc index 46694ad..d4b56d2 100644 --- a/src/sim/id.cc +++ b/src/sim/id.cc @@ -116,8 +116,8 @@ void ID::decode_I_type( s0b = REG_SIZE; s1b = s0b + REG_SIZE; - s2b = WORD_SPEC; - s3 = GET_MID_BITS(s1, s1b, s2b); + s2b = WORD_SPEC - LINE_SPEC - OPCODE_SIZE; + s3 = GET_BITS_SIGN_EXTEND(s1, s1b, s2b); s2 = GET_MID_BITS(s1, s0b, s1b); s1 = GET_LS_BITS(s1, s0b); @@ -135,19 +135,20 @@ void ID::decode_J_type(signed int &s1, signed int &s2, signed int &s3) unsigned int s0b, s1b; s0b = REG_SIZE; - s1b = WORD_SPEC; + s1b = WORD_SPEC - LINE_SPEC - OPCODE_SIZE; s3 = 0; - s2 = GET_MID_BITS(s1, s0b, s1b); + s2 = GET_BITS_SIGN_EXTEND(s1, s0b, s1b); s1 = GET_LS_BITS(s1, s0b); + std::cout << "s1: " << s1 << ", s2: " << s2 << ", s3: " << s3 << std::endl; this->status = this->read_guard(*&s1); } -std::vector ID::stage_info() { +std::vector ID::stage_info() { std::vector info; if(this->curr_instr){ info.push_back(this->curr_instr->get_pc()); info.push_back(this->curr_instr->get_instr_bits()); - } + } return info; } diff --git a/tests/controller.cc b/tests/controller.cc index 74284b7..6920933 100644 --- a/tests/controller.cc +++ b/tests/controller.cc @@ -311,7 +311,7 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") CHECK(i->get_time_of(MEM) == 28); CHECK(i->get_time_of(WRITE) == 29); CHECK(i->get_s1() == 0x8); - CHECK(i->get_s2() == 0b111111111111111111001); + CHECK(i->get_s2() == 0xfffffff9); CHECK(this->ct->get_gprs().at(2) == 0x200); CHECK(this->ct->get_gprs().at(5) == 0x0); CHECK(this->ct->get_gprs().at(6) == 0x1); diff --git a/tests/id.cc b/tests/id.cc index b8d0479..5af15fc 100644 --- a/tests/id.cc +++ b/tests/id.cc @@ -185,7 +185,7 @@ TEST_CASE_METHOD(IDFixture, "Parse arbitrary j-type # two", "[id]") i = this->decode_bits(t); CHECK(i->get_s1() == 0x00000000); // registers are empty - CHECK(i->get_s2() == 0xBBCCF); + CHECK(i->get_s2() == 0xFFFBBCCF); CHECK(i->get_mnemonic() == JAL); delete i; -- cgit v1.2.3 From 94a0435da91501d2320d6081c552cb5df0c4433d Mon Sep 17 00:00:00 2001 From: bd Date: Thu, 17 Apr 2025 01:17:48 -0400 Subject: Keep track of checked out in DTO to simplify wb cond logic (bug) --- gui/worker.cc | 12 ++++---- inc/id.h | 2 +- inc/instrDTO.h | 29 +++++++++---------- src/sim/dum.cc | 1 - src/sim/id.cc | 9 +++++- src/sim/if.cc | 5 ++-- src/sim/instrDTO.cc | 12 +++++--- src/sim/stage.cc | 1 - src/sim/wb.cc | 17 ++++------- tests/controller.cc | 81 ----------------------------------------------------- tests/id.cc | 10 +++---- tests/if.cc | 4 --- 12 files changed, 49 insertions(+), 134 deletions(-) (limited to 'tests/controller.cc') diff --git a/gui/worker.cc b/gui/worker.cc index 3825395..9202b89 100644 --- a/gui/worker.cc +++ b/gui/worker.cc @@ -16,7 +16,7 @@ void Worker::doWork() emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc()); emit dram_storage(this->d->view(0, 32)); - emit cache_storage(this->c->view(0, 8)); + emit cache_storage(this->c->view(0, 7)); emit register_storage(this->ct->get_gprs()); signed int b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, @@ -44,10 +44,10 @@ void Worker::doWork() b17 = 0b00000000000000010010100101001101; b18 = 0b00000000000000000101001101000000; b19 = 0b11111111111111111100100000010110; - b20 = 0b00000000000000000000000000010000; + // b20 = 0b00000000000000000000000000010000; p = {b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, - b11, b12, b13, b14, b15, b16, b17, b18, b19, b20}; + b11, b12, b13, b14, b15, b16, b17, b18, b19}; this->d->load(p); } @@ -69,7 +69,7 @@ void Worker::refreshDram() void Worker::refreshCache() { qDebug() << "Refreshing Dram"; - emit cache_storage(this->c->view(0, 8)); + emit cache_storage(this->c->view(0, 7)); } void Worker::refreshRegisters() @@ -83,7 +83,7 @@ void Worker::runSteps(int steps) qDebug() << "Running for steps: " << steps; this->ct->run_for(steps); emit dram_storage(this->d->view(0, 256)); - emit cache_storage(this->c->view(0, 8)); + emit cache_storage(this->c->view(0, 7)); emit register_storage(this->ct->get_gprs()); emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc()); emit if_info(this->if_stage->stage_info()); @@ -98,7 +98,7 @@ void Worker::runStep() qDebug() << "Running for 1 step "; this->ct->advance(WAIT); emit dram_storage(this->d->view(0, 256)); - emit cache_storage(this->c->view(0, 8)); + emit cache_storage(this->c->view(0, 7)); emit register_storage(this->ct->get_gprs()); emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc()); emit if_info(this->if_stage->stage_info()); diff --git a/inc/id.h b/inc/id.h index db22d7d..ed13771 100644 --- a/inc/id.h +++ b/inc/id.h @@ -41,7 +41,6 @@ class ID : public Stage std::vector stage_info() override; private: - void advance_helper() override; /** * Helper for `get_instr_fields` * Attempts to parse and dereference instruction arguments. Uses read and @@ -52,6 +51,7 @@ class ID : public Stage * @param the resulting second field. * @param the resulting third field. */ + void advance_helper() override; /** * Parse an instruction into a type, opcode, and fields. If the type is * invalid, only the type field will be set. diff --git a/inc/instrDTO.h b/inc/instrDTO.h index b6dec06..755ab9f 100644 --- a/inc/instrDTO.h +++ b/inc/instrDTO.h @@ -15,18 +15,15 @@ class InstrDTO InstrDTO(); ~InstrDTO() = default; - /** - * @return hist entry for Accessor - */ - int get_time_of(Accessor); - /** - * @return id_cycle - */ int get_id_cycle(); /** * @return instr_bits */ signed int get_instr_bits(); + /** + * @return checked_out + */ + signed int get_checked_out(); /** * @return s1 */ @@ -52,14 +49,14 @@ class InstrDTO */ unsigned int get_pc(); - /** - * @param set hist key - */ - void set_time_of(Accessor, int); /** * @param instr_bits */ void set_instr_bits(signed int); + /** + * @param checked_out + */ + void set_checked_out(signed int); /** * @param s1 */ @@ -87,14 +84,16 @@ class InstrDTO void set_pc(unsigned int pc); private: - /** - * The clock cycle each stage finished an operation. - */ - std::unordered_map hist; /** * The raw bits encoding the instruction. */ signed int instr_bits; + /** + * The register, if any, this instruction has checked out. A checked out + * register cannot be checked out by another register. This prevents RAW + * conflicts. + */ + signed int checked_out; /** * Slots in this instruction, for storing temporary registers, immediates, * or other. diff --git a/src/sim/dum.cc b/src/sim/dum.cc index f712fce..ab4eaa4 100644 --- a/src/sim/dum.cc +++ b/src/sim/dum.cc @@ -11,7 +11,6 @@ InstrDTO *DUM::advance(Response p) InstrDTO *r = nullptr; if (this->curr_instr && p == WAIT) { - this->curr_instr->set_time_of(this->id, this->clock_cycle); r = new InstrDTO(*this->curr_instr); delete this->curr_instr; curr_instr = nullptr; diff --git a/src/sim/id.cc b/src/sim/id.cc index d4b56d2..3d5baef 100644 --- a/src/sim/id.cc +++ b/src/sim/id.cc @@ -38,7 +38,14 @@ Response ID::read_guard(signed int &v) void ID::write_guard(signed int &v) { - this->checked_out.push_back(v); + // zero register shouldn't be written. + if (v != 0) { + // keep track in the instrDTO for displaying to user and writeback + // keep track in checked_out so we can still access this information! + this->checked_out.push_back(v); + this->curr_instr->set_checked_out(v); + std::cout << "checked out: " << v << std::endl; + } v = this->dereference_register(v); } diff --git a/src/sim/if.cc b/src/sim/if.cc index fb49749..1223149 100644 --- a/src/sim/if.cc +++ b/src/sim/if.cc @@ -14,7 +14,6 @@ InstrDTO *IF::advance(Response p) if (this->curr_instr != nullptr && p == WAIT) { // mutual consent ++this->pc; - this->curr_instr->set_time_of(this->id, this->clock_cycle); r = new InstrDTO(*this->curr_instr); delete curr_instr; curr_instr = nullptr; @@ -23,12 +22,12 @@ InstrDTO *IF::advance(Response p) return r; } -std::vector IF::stage_info() { +std::vector IF::stage_info() { std::vector info; if(this->curr_instr){ info.push_back(this->curr_instr->get_pc()); info.push_back(this->curr_instr->get_instr_bits()); - } + } return info; } diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc index aa49b7e..a82ef28 100644 --- a/src/sim/instrDTO.cc +++ b/src/sim/instrDTO.cc @@ -4,6 +4,7 @@ InstrDTO::InstrDTO() { this->instr_bits = 0; + this->checked_out = -1; this->s1 = 0; this->s2 = 0; this->s3 = 0; @@ -12,10 +13,10 @@ InstrDTO::InstrDTO() this->pc = 0; } -int InstrDTO::get_time_of(Accessor a) { return this->hist[a]; } - signed int InstrDTO::get_instr_bits() { return this->instr_bits; } +signed int InstrDTO::get_checked_out() { return this->checked_out; } + signed int InstrDTO::get_s1() { return this->s1; } signed int InstrDTO::get_s2() { return this->s2; } @@ -28,10 +29,13 @@ Type InstrDTO::get_type() { return this->type; } unsigned int InstrDTO::get_pc() { return this->pc; } -void InstrDTO::set_time_of(Accessor a, int i) { this->hist[a] = i; } - void InstrDTO::set_instr_bits(signed int instr) { this->instr_bits = instr; } +void InstrDTO::set_checked_out(signed int checked_out) +{ + this->checked_out = checked_out; +} + void InstrDTO::set_s1(signed int s) { this->s1 = s; } void InstrDTO::set_s2(signed int s) { this->s2 = s; } diff --git a/src/sim/stage.cc b/src/sim/stage.cc index b7926fd..7df1dba 100644 --- a/src/sim/stage.cc +++ b/src/sim/stage.cc @@ -38,7 +38,6 @@ InstrDTO *Stage::advance(Response p) } if (this->status == OK && p == WAIT && this->curr_instr) { // mutual consent - this->curr_instr->set_time_of(this->id, this->clock_cycle); r = new InstrDTO(*this->curr_instr); delete curr_instr; curr_instr = nullptr; diff --git a/src/sim/wb.cc b/src/sim/wb.cc index 01768e8..3fa7dd3 100644 --- a/src/sim/wb.cc +++ b/src/sim/wb.cc @@ -3,6 +3,8 @@ #include "instrDTO.h" #include "response.h" #include "stage.h" +#include +#include WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; } @@ -10,7 +12,7 @@ void WB::advance_helper() { if (this->curr_instr->get_mnemonic() != NOP && this->curr_instr->get_type() != INV) { - if (this->should_write()) + if (this->curr_instr->get_checked_out() > 0) this->write_handler(); else if (this->should_jump()) this->jump_handler(); @@ -26,8 +28,9 @@ void WB::write_handler() throw std::runtime_error("instruction tried to pop a register out of " "an empty queue during writeback."); - reg = this->checked_out.front(); this->checked_out.pop_front(); + reg = this->curr_instr->get_checked_out(); + std::cout << "checked in: " << reg << std::endl; this->store_register(reg, this->curr_instr->get_s1()); } @@ -49,13 +52,3 @@ bool WB::should_jump() t = this->curr_instr->get_type(); return t == J; } - -bool WB::should_write() -{ - Mnemonic m; - Type t; - - m = this->curr_instr->get_mnemonic(); - t = this->curr_instr->get_type(); - return (t == R || t == I) && (m != STORE && m != STOREV); -} diff --git a/tests/controller.cc b/tests/controller.cc index 6920933..59f1d81 100644 --- a/tests/controller.cc +++ b/tests/controller.cc @@ -107,11 +107,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 3); - CHECK(i->get_time_of(DCDE) == 4); - CHECK(i->get_time_of(EXEC) == 5); - CHECK(i->get_time_of(MEM) == 6); - CHECK(i->get_time_of(WRITE) == 7); CHECK(i->get_s1() == 0x200); CHECK(i->get_s2() == 0x0); CHECK(i->get_s3() == 0x200); @@ -124,11 +119,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 4); - CHECK(i->get_time_of(DCDE) == 5); - CHECK(i->get_time_of(EXEC) == 6); - CHECK(i->get_time_of(MEM) == 7); - CHECK(i->get_time_of(WRITE) == 8); CHECK(i->get_s1() == 0x1); CHECK(i->get_s2() == 0x0); CHECK(i->get_s3() == 0x1); @@ -152,13 +142,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 5); - CHECK( - i->get_time_of(DCDE) == - 8); // the previous conflicting instruction wrote here! - CHECK(i->get_time_of(EXEC) == 9); - CHECK(i->get_time_of(MEM) == 14); // waited for fetch + 3 dram - CHECK(i->get_time_of(WRITE) == 15); CHECK(i->get_s1() == 0x200); CHECK(i->get_s2() == 0x1); CHECK(i->get_s3() == 0x0); @@ -173,11 +156,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 8); - CHECK(i->get_time_of(DCDE) == 9); - CHECK(i->get_time_of(EXEC) == 14); - CHECK(i->get_time_of(MEM) == 15); - CHECK(i->get_time_of(WRITE) == 16); CHECK(i->get_s1() == 0x2); CHECK(i->get_s2() == 0x1); // the previous value in the destination register CHECK(i->get_s3() == 0x2); @@ -194,13 +172,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 14); // fetching new line + mem - CHECK( - i->get_time_of(DCDE) == - 16); // the previous conflicting instruction wrote here! - CHECK(i->get_time_of(EXEC) == 17); - CHECK(i->get_time_of(MEM) == 18); - CHECK(i->get_time_of(WRITE) == 19); CHECK(i->get_s1() == 0x201); CHECK(i->get_s2() == 0x2); // address CHECK(i->get_s3() == 0x1); // offset @@ -215,11 +186,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 16); - CHECK(i->get_time_of(DCDE) == 17); - CHECK(i->get_time_of(EXEC) == 18); - CHECK(i->get_time_of(MEM) == 19); - CHECK(i->get_time_of(WRITE) == 20); CHECK(i->get_s1() == 0x0); CHECK(i->get_s2() == 0x2); CHECK(i->get_s3() == 0x0); @@ -232,11 +198,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 17); - CHECK(i->get_time_of(DCDE) == 18); - CHECK(i->get_time_of(EXEC) == 19); - CHECK(i->get_time_of(MEM) == 20); - CHECK(i->get_time_of(WRITE) == 21); CHECK(i->get_s1() == 0x1); CHECK(i->get_s2() == 0x0); CHECK(i->get_s3() == 0x1); @@ -251,11 +212,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 18); - CHECK(i->get_time_of(DCDE) == 19); - CHECK(i->get_time_of(EXEC) == 20); - CHECK(i->get_time_of(MEM) == 21); - CHECK(i->get_time_of(WRITE) == 22); CHECK(i->get_s1() == 0xE); CHECK(i->get_s2() == 0x7); CHECK(this->ct->get_gprs().at(2) == 0x200); @@ -283,13 +239,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK( - i->get_time_of(FETCH) == - 24); // 6 greater than last fetch (4 flush pipe, 2 dram) - CHECK(i->get_time_of(DCDE) == 25); - CHECK(i->get_time_of(EXEC) == 26); - CHECK(i->get_time_of(MEM) == 27); - CHECK(i->get_time_of(WRITE) == 28); CHECK(i->get_s1() == 0x1); CHECK(i->get_s2() == 0x0); CHECK(i->get_s3() == 0x0); @@ -305,11 +254,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 25); - CHECK(i->get_time_of(DCDE) == 26); - CHECK(i->get_time_of(EXEC) == 27); - CHECK(i->get_time_of(MEM) == 28); - CHECK(i->get_time_of(WRITE) == 29); CHECK(i->get_s1() == 0x8); CHECK(i->get_s2() == 0xfffffff9); CHECK(this->ct->get_gprs().at(2) == 0x200); @@ -335,11 +279,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); // it was already in cache - CHECK(i->get_time_of(FETCH) == 29); // clear out pipe (4) - CHECK(i->get_time_of(DCDE) == 30); - CHECK(i->get_time_of(EXEC) == 31); - CHECK(i->get_time_of(MEM) == 32); - CHECK(i->get_time_of(WRITE) == 33); CHECK(i->get_s1() == 0x200); CHECK(i->get_s2() == 0x0); CHECK(i->get_s3() == 0x0); @@ -360,11 +299,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 30); - CHECK(i->get_time_of(DCDE) == 33); - CHECK(i->get_time_of(EXEC) == 34); - CHECK(i->get_time_of(MEM) == 35); - CHECK(i->get_time_of(WRITE) == 36); CHECK(i->get_s1() == 0x1); CHECK(i->get_s2() == 0x0); CHECK(i->get_s3() == 0x0); @@ -380,11 +314,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 33); - CHECK(i->get_time_of(DCDE) == 34); - CHECK(i->get_time_of(EXEC) == 35); - CHECK(i->get_time_of(MEM) == 36); - CHECK(i->get_time_of(WRITE) == 37); CHECK(i->get_s1() == 0x2); CHECK(i->get_s2() == 0x0); CHECK(i->get_s3() == 0x1); @@ -405,11 +334,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 34); - CHECK(i->get_time_of(DCDE) == 37); - CHECK(i->get_time_of(EXEC) == 38); - CHECK(i->get_time_of(MEM) == 39); - CHECK(i->get_time_of(WRITE) == 40); CHECK(i->get_s1() == 0x3); CHECK(i->get_s2() == 0x2); CHECK(i->get_s3() == 0x1); @@ -429,11 +353,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == 37); - CHECK(i->get_time_of(DCDE) == 40); - CHECK(i->get_time_of(EXEC) == 41); - CHECK(i->get_time_of(MEM) == 42); - CHECK(i->get_time_of(WRITE) == 43); CHECK(i->get_s1() == 0x200); CHECK(i->get_s2() == 0x3); CHECK(i->get_s3() == 0x0); diff --git a/tests/id.cc b/tests/id.cc index 5af15fc..06eec0c 100644 --- a/tests/id.cc +++ b/tests/id.cc @@ -140,7 +140,7 @@ TEST_CASE_METHOD(IDFixture, "Parse arbitrary i-type # one", "[id]") CHECK(i->get_s1() == 0x00000000); // registers are empty CHECK(i->get_s2() == 0x00000000); CHECK(i->get_s3() == 0xF); - CHECK(i->get_mnemonic() == SFTLI); + CHECK(i->get_mnemonic() == ANDI); delete i; } @@ -156,7 +156,7 @@ TEST_CASE_METHOD(IDFixture, "Parse arbitrary i-type # two", "[id]") CHECK(i->get_s1() == 0x00000000); // registers are empty CHECK(i->get_s2() == 0x00000000); CHECK(i->get_s3() == 0xCC); - CHECK(i->get_mnemonic() == STORE); + CHECK(i->get_mnemonic() == STOREV); delete i; } @@ -254,7 +254,7 @@ TEST_CASE_METHOD(IDFixture, "stores indefinite conflicts", "[id]") signed int v, ov; Response r; - v = 0b0; + v = 0b1; ov = v; while (v < 0b110) { this->d->write_guard(v); @@ -269,8 +269,8 @@ TEST_CASE_METHOD(IDFixture, "stores indefinite conflicts", "[id]") CHECK(v == 0b110); REQUIRE(r == STALLED); - v = 0b0; + v = 0b1; r = this->d->read_guard(v); - CHECK(v == 0b0); + CHECK(v == 0b1); REQUIRE(r == STALLED); } diff --git a/tests/if.cc b/tests/if.cc index 5ccd73b..01070ef 100644 --- a/tests/if.cc +++ b/tests/if.cc @@ -77,7 +77,6 @@ TEST_CASE_METHOD(IFFixture, "fetch returns single instuction", "[if_pipe]") expected_cycles = this->m_delay + this->c_delay + 2; i = this->fetch_through(); - CHECK(i->get_time_of(FETCH) == expected_cycles); REQUIRE(i->get_instr_bits() == this->p[0]); delete i; @@ -91,14 +90,12 @@ TEST_CASE_METHOD(IFFixture, "fetch returns two instuctions", "[if_pipe]") expected_cycles = this->m_delay + this->c_delay + 2; i = this->fetch_through(); - CHECK(i->get_time_of(FETCH) == expected_cycles); REQUIRE(i->get_instr_bits() == this->p[0]); delete i; expected_cycles += this->c_delay + 1; i = this->fetch_cache(); - CHECK(i->get_time_of(FETCH) == expected_cycles); REQUIRE(i->get_instr_bits() == this->p[1]); delete i; } @@ -129,7 +126,6 @@ TEST_CASE_METHOD(IFFixture, "fetch waits with old instruction", "[if_pipe]") i = this->ct->advance(WAIT); REQUIRE(i != nullptr); - CHECK(i->get_time_of(FETCH) == expected_cycles); REQUIRE(i->get_instr_bits() == this->p[0]); delete i; -- cgit v1.2.3