From 6579f7272905d1e25b43ef051da6c2180e60ca2b Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Tue, 1 Apr 2025 00:49:52 -0400
Subject: Ensure all stages only do work if they are not 'OK'

---
 tests/controller.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'tests/controller.cc')

diff --git a/tests/controller.cc b/tests/controller.cc
index de49629..f6d9b25 100644
--- a/tests/controller.cc
+++ b/tests/controller.cc
@@ -62,19 +62,19 @@ TEST_CASE_METHOD(ControllerPipeFixture, "Add until exec", "[tmp]")
 	this->d->load(p);
 
 	// dram
-	i = this->ct->advance(OK);
+	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
 	// fetch
-	i = this->ct->advance(OK);
+	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
 	// decode
-	i = this->ct->advance(OK);
+	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
 	// exec
-	i = this->ct->advance(OK);
+	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
 	// done
-	i = this->ct->advance(OK);
+	i = this->ct->advance(WAIT);
 	REQUIRE(i != nullptr);
 
 	CHECK(i->get_time_of(FETCH) == 3);
-- 
cgit v1.2.3


From 25ce77db5f0dbfe6064eb0553591f1b956bad24a Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Tue, 1 Apr 2025 15:57:14 -0400
Subject: Fix a lot of pipeline bugs

---
 inc/stage.h         |   6 +
 inc/wb.h            |  20 +++-
 src/sim/ex.cc       |  14 ++-
 src/sim/id.cc       |  20 ++--
 src/sim/instrDTO.cc |   2 +-
 src/sim/mm.cc       |   1 +
 src/sim/stage.cc    |  25 +++-
 src/sim/wb.cc       |  75 +++++++-----
 tests/controller.cc | 111 +++++++++++++++---
 tests/id.cc         | 320 ++++++++++++++++++++++++++--------------------------
 10 files changed, 371 insertions(+), 223 deletions(-)

(limited to 'tests/controller.cc')

diff --git a/inc/stage.h b/inc/stage.h
index 2f9812f..87ee9c1 100644
--- a/inc/stage.h
+++ b/inc/stage.h
@@ -80,6 +80,12 @@ class Stage
 	 * @return true if registers are not in checked_out, false otherwise.
 	 */
 	bool is_checked_out(signed int r);
+	/**
+	 * Stores `d` into the register indexed `v`.
+	 * @param the register number.
+	 * @param the value to store.
+	 */
+	void store_register(signed int v, signed int d);
 	/**
 	 * Returns the value of the register corresponding to `v`.
 	 * @param the register number.
diff --git a/inc/wb.h b/inc/wb.h
index 62cef17..c4755ea 100644
--- a/inc/wb.h
+++ b/inc/wb.h
@@ -14,9 +14,27 @@ class WB : public Stage
 	 */
 	WB(Stage *next);
 	using Stage::advance;
-	
+
   private:
 	void advance_helper() override;
+	/**
+	 * Performs the actual work of storing into a register.
+	 */
+	void write_handler();
+	/**
+	 * Performs the actual work of processing a jump instruction.
+	 */
+	void jump_handler();
+	/**
+	 * @return true if the current instruction is an R or I type and is not a
+	 * STORE.
+	 */
+	bool should_write();
+	/**
+	 * @return true if the current instruction is a J type and is not a push.
+	 * STORE.
+	 */
+	bool should_jump();
 };
 
 #endif /* WB_H_INCLUDED */
diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index 3d95917..ec4c47f 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -4,6 +4,7 @@
 #include "instrDTO.h"
 #include "response.h"
 #include "stage.h"
+#include "utils.h"
 #include <unordered_map>
 
 // clang-format off
@@ -185,6 +186,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			ADDI,
 			{
 				s1 = s1 + s3;
+				std::cout << "= " << s2 << std::endl;
 				(void)s2;
 				(void)this;
 			}),
@@ -282,28 +284,32 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			BEQ,
 			{
-				(this->get_condition(EQ)) ? s1 = this->pc + s2 : s1 = this->pc;
+				(this->get_condition(EQ)) ? s1 = wrap_address(this->pc + s2)
+										  : s1 = -1;
 				(void)s3;
 			}),
 
 		INIT_INSTRUCTION(
 			BGT,
 			{
-				(this->get_condition(GT)) ? s1 = this->pc + s2 : s1 = this->pc;
+				(this->get_condition(GT)) ? s1 = wrap_address(this->pc + s2)
+										  : s1 = -1;
 				(void)s3;
 			}),
 
 		INIT_INSTRUCTION(
 			BUF,
 			{
-				(this->get_condition(UF)) ? s1 = this->pc + s2 : s1 = this->pc;
+				(this->get_condition(UF)) ? s1 = wrap_address(this->pc) + s2
+										  : s1 = -1;
 				(void)s3;
 			}),
 
 		INIT_INSTRUCTION(
 			BOF,
 			{
-				(this->get_condition(OF)) ? s1 = this->pc + s2 : s1 = this->pc;
+				(this->get_condition(OF)) ? s1 = wrap_address(this->pc + s2)
+										  : s1 = -1;
 				(void)s3;
 			}),
 
diff --git a/src/sim/id.cc b/src/sim/id.cc
index 4a55d04..ddac35b 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -48,14 +48,18 @@ void ID::advance_helper()
 	Mnemonic m;
 	Type t;
 
-	s1 = curr_instr->get_instr_bits();
-	get_instr_fields(s1, s2, s3, m, t);
-	if (this->status == OK) {
-		curr_instr->set_s1(s1);
-		curr_instr->set_s2(s2);
-		curr_instr->set_s3(s3);
-		curr_instr->set_mnemonic(m);
-		curr_instr->set_type(t);
+	if (curr_instr->get_mnemonic() == NOP)
+		this->status = OK;
+	else {
+		s1 = curr_instr->get_instr_bits();
+		get_instr_fields(s1, s2, s3, m, t);
+		if (this->status == OK) {
+			curr_instr->set_s1(s1);
+			curr_instr->set_s2(s2);
+			curr_instr->set_s3(s3);
+			curr_instr->set_mnemonic(m);
+			curr_instr->set_type(t);
+		}
 	}
 }
 
diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc
index 28364b7..7324ba9 100644
--- a/src/sim/instrDTO.cc
+++ b/src/sim/instrDTO.cc
@@ -7,7 +7,7 @@ InstrDTO::InstrDTO()
 	this->s1 = 0;
 	this->s2 = 0;
 	this->s3 = 0;
-	this->mnemonic = NOP;
+	this->mnemonic = ADD;
 	this->type = INV;
 }
 
diff --git a/src/sim/mm.cc b/src/sim/mm.cc
index c83ae7d..e29bf90 100644
--- a/src/sim/mm.cc
+++ b/src/sim/mm.cc
@@ -10,6 +10,7 @@ void MM::advance_helper()
 {
 	signed int data;
 
+	std::cout << "mem" << this->curr_instr->get_s2() << std::endl;
 	switch (this->curr_instr->get_mnemonic()) {
 	case LOAD:
 		this->status = this->storage->read_word(
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 31d7d0d..b10a206 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -2,7 +2,6 @@
 #include "utils.h"
 #include <array>
 #include <deque>
-#include <iostream>
 
 Stage::Stage(Stage *next)
 {
@@ -28,10 +27,12 @@ void Stage::set_pc(unsigned int pc) { this->pc = pc; }
 InstrDTO *Stage::advance(Response p)
 {
 	InstrDTO *r = nullptr;
+	InstrDTO *s = nullptr;
 	Response n;
 
-	if (this->curr_instr && this->status != OK)
+	if (this->curr_instr && this->status != OK) {
 		this->advance_helper();
+	}
 	if (this->status == OK && p == WAIT && this->curr_instr) {
 		// mutual consent
 		this->curr_instr->set_time_of(this->id, this->clock_cycle);
@@ -42,8 +43,9 @@ InstrDTO *Stage::advance(Response p)
 	}
 
 	n = (p != WAIT || this->status != WAIT) ? STALLED : WAIT;
-	// the power of consent
-	this->curr_instr = this->next->advance(n);
+	s = this->next->advance(n);
+	if (s)
+		this->curr_instr = s;
 	return r;
 }
 
@@ -70,6 +72,21 @@ signed int Stage::dereference_register(signed int v)
 	return r;
 }
 
+void Stage::store_register(signed int v, signed int d)
+{
+	if (v < 0 || v >= GPR_NUM + V_NUM) {
+		throw std::out_of_range(string_format(
+			"instruction tried to access register %d, which does "
+			"not exist",
+			v));
+	}
+
+	if (v >= GPR_NUM)
+		this->vrs[v % GPR_NUM] = d;
+	else
+		this->gprs[v] = d;
+}
+
 bool Stage::is_checked_out(signed int r)
 {
 	return std::find(this->checked_out.begin(), this->checked_out.end(), r) !=
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 276d1d0..01768e8 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -8,33 +8,54 @@ WB::WB(Stage *stage) : Stage(stage) { this->id = WRITE; }
 
 void WB::advance_helper()
 {
-	if (this->curr_instr->get_type() == R ||
-		this->curr_instr->get_type() == I) {
-		if (this->checked_out.size() > 0) {
-			signed int reg = this->checked_out.front();
-			this->checked_out.pop_front();
-			if (reg >= GPR_NUM) {
-				// TODO: handle vector instructions
-			} else {
-				if (this->curr_instr->get_mnemonic() != STORE &&
-					this->curr_instr->get_mnemonic() != STOREV) {
-					this->gprs[reg] = this->curr_instr->get_s1();
-				}
-			}
-		}
-	} else if (this->curr_instr->get_type() == J) {
-		// TODO:handle push pop
-		// branch taken
-		if (this->pc != this->curr_instr->get_s1()) {
-			if (this->curr_instr->get_mnemonic() == JAL) {
-				// set link register to next instruction
-				this->gprs[1] = this->pc + 1;
-			}
-			this->pc = this->curr_instr->get_s1();
-			// clear pending registers and squash pipeline
-			this->checked_out = {};
-			this->next->squash();
-		}
+	if (this->curr_instr->get_mnemonic() != NOP &&
+		this->curr_instr->get_type() != INV) {
+		if (this->should_write())
+			this->write_handler();
+		else if (this->should_jump())
+			this->jump_handler();
 	}
 	this->status = OK;
 }
+
+void WB::write_handler()
+{
+	signed int reg;
+
+	if (this->checked_out.size() < 1)
+		throw std::runtime_error("instruction tried to pop a register out of "
+								 "an empty queue during writeback.");
+
+	reg = this->checked_out.front();
+	this->checked_out.pop_front();
+	this->store_register(reg, this->curr_instr->get_s1());
+}
+
+void WB::jump_handler()
+{
+	if (this->curr_instr->get_s1() > 0) {
+		if (this->curr_instr->get_mnemonic() == JAL)
+			this->gprs[1] = this->pc + 1;
+		this->pc = this->curr_instr->get_s1();
+		this->checked_out = {};
+		this->next->squash();
+	}
+}
+
+bool WB::should_jump()
+{
+	Type t;
+
+	t = this->curr_instr->get_type();
+	return t == J;
+}
+
+bool WB::should_write()
+{
+	Mnemonic m;
+	Type t;
+
+	m = this->curr_instr->get_mnemonic();
+	t = this->curr_instr->get_type();
+	return (t == R || t == I) && (m != STORE && m != STOREV);
+}
diff --git a/tests/controller.cc b/tests/controller.cc
index f6d9b25..f2ef3de 100644
--- a/tests/controller.cc
+++ b/tests/controller.cc
@@ -21,15 +21,27 @@ class ControllerPipeFixture
 		IF *f = new IF(nullptr);
 		ID *d = new ID(f);
 		EX *e = new EX(d);
+		MM *m = new MM(e);
+		WB *w = new WB(m);
+		this->stage_num = 5;
 
-		this->ct = new Controller(e, this->c, true);
+		this->ct = new Controller(w, this->c, true);
 	}
 	~ControllerPipeFixture()
 	{
 		delete this->ct;
 		delete this->c;
 	};
-
+	void fill_pipe()
+	{
+		InstrDTO *i = nullptr;
+		int j;
+		for (j = 0; j < this->stage_num + 1; ++j) {
+			i = this->ct->advance(WAIT);
+			REQUIRE(i == nullptr);
+		}
+	}
+	int stage_num;
 	Cache *c;
 	Dram *d;
 	Controller *ct;
@@ -51,40 +63,103 @@ TEST_CASE_METHOD(
 	CHECK(this->ct->get_pc() == 0);
 }
 
-TEST_CASE_METHOD(ControllerPipeFixture, "Add until exec", "[tmp]")
+TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 {
-	signed int b;
+	signed int b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11;
 	std::vector<signed int> p;
 	InstrDTO *i;
 
-	b = 0b1010100000000001001101;
-	p = {b};
+	// I-TYPE              /    /    /   /
+	b0 = 0b00000010000000000001000000001101; // ADDI $sp $0 0x200;
+	b1 = 0b00000000000000010010100000001101; // ADDI $5 $0 0x1;
+	b2 = 0b00000000000000000001000101101101; // STORE $5 0($sp);  (RAW HAZARD)!
+	// I-TYPE              /    /    /   /
+	b3 = 0b00000000000000100010100000001101; // ADDI $5 $0 0x2;   (RAW HAZARD)!
+	b4 = 0b00000000000000010001000101101101; // STORE $5 1($sp);  (RAW HAZARD)!
+	// // I-TYPE              /    /    /   /
+	// b9 = 0b00000000000000000010100000001101;  // ADDI $5 $0 0x0;
+	// // I-TYPE               /    /    /   /
+	// b10 = 0b00000000000000110011000000001101; // ADDI $6 $0 0x3;
+	// // J-TYPE                    /    /   /
+	// b11 = 0b00000000000000000011100000001010; // jrl CHECK
+
+	p = {b0, b1, b2, b3};
 	this->d->load(p);
 
-	// dram
+	this->fill_pipe();
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 3);
+	CHECK(i->get_time_of(DCDE) == 4);
+	CHECK(i->get_time_of(EXEC) == 5);
+	CHECK(i->get_time_of(MEM) == 6);
+	CHECK(i->get_time_of(WRITE) == 7);
+	CHECK(i->get_s1() == 0x200);
+	CHECK(i->get_s2() == 0x0);
+	CHECK(i->get_s3() == 0x200);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(i->get_mnemonic() == ADDI);
+	CHECK(i->get_instr_bits() == b0);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 4);
+	CHECK(i->get_time_of(DCDE) == 5);
+	CHECK(i->get_time_of(EXEC) == 6);
+	CHECK(i->get_time_of(MEM) == 7);
+	CHECK(i->get_time_of(WRITE) == 8);
+	CHECK(i->get_s1() == 0x1);
+	CHECK(i->get_s2() == 0x0);
+	CHECK(i->get_s3() == 0x1);
+	CHECK(this->ct->get_gprs().at(5) == 0x1);
+	CHECK(i->get_mnemonic() == ADDI);
+	CHECK(i->get_instr_bits() == b1);
+
+	delete i;
 	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
-	// fetch
 	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
-	// decode
 	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
-	// exec
 	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
-	// done
 	i = this->ct->advance(WAIT);
 	REQUIRE(i != nullptr);
 
-	CHECK(i->get_time_of(FETCH) == 3);
-	CHECK(i->get_time_of(DCDE) == 4);
-	CHECK(i->get_time_of(EXEC) == 5);
-	CHECK(i->get_s1() == 42);
-	CHECK(i->get_s2() == 0);
-	CHECK(i->get_s3() == 42);
+	CHECK(i->get_time_of(FETCH) == 5);
+	CHECK(i->get_time_of(DCDE) == 8); // the previous conflicting instruction wrote here!
+	CHECK(i->get_time_of(EXEC) == 9);
+	CHECK(i->get_time_of(MEM) == 12); // waited for fetch + 2 dram
+	CHECK(i->get_time_of(WRITE) == 13);
+	CHECK(i->get_s1() == 0x1);
+	CHECK(i->get_s2() == 0x200);
+	CHECK(i->get_s3() == 0x0);
+	// NO STORE
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(5) == 0x1);
+	CHECK(i->get_mnemonic() == STORE);
+	CHECK(i->get_instr_bits() == b2);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 8);
+	CHECK(i->get_time_of(DCDE) == 9);
+	CHECK(i->get_time_of(EXEC) == 12);
+	CHECK(i->get_time_of(MEM) == 13);
+	CHECK(i->get_time_of(WRITE) == 14);
+	CHECK(i->get_s1() == 0x2);
+	CHECK(i->get_s2() == 0x0);
+	CHECK(i->get_s3() == 0x2);
+	// NO STORE
+	CHECK(this->ct->get_gprs().at(5) == 0x2);
 	CHECK(i->get_mnemonic() == ADDI);
-	CHECK(i->get_instr_bits() == b);
+	CHECK(i->get_instr_bits() == b3);
 
 	delete i;
 }
diff --git a/tests/id.cc b/tests/id.cc
index 7d5e05d..77a7cd9 100644
--- a/tests/id.cc
+++ b/tests/id.cc
@@ -84,18 +84,18 @@ class IDFixture
 	Controller *ct;
 };
 
-// TEST_CASE_METHOD(IDFixture, "Parse invalid type", "[id]")
-// {
-// 	signed int t;
-// 	InstrDTO *i;
+TEST_CASE_METHOD(IDFixture, "Parse invalid type", "[id]")
+{
+	signed int t;
+	InstrDTO *i;
 
-// 	t = this->encode_R_type(0b0, 0b1, 0b10, 0b11, 0b11);
-// 	i = this->decode_bits(t);
+	t = this->encode_R_type(0b0, 0b1, 0b10, 0b11, 0b11);
+	i = this->decode_bits(t);
 
-// 	CHECK(i->get_mnemonic() == NOP);
+	CHECK(i->get_mnemonic() == NOP);
 
-// 	delete i;
-// }
+	delete i;
+}
 
 TEST_CASE_METHOD(IDFixture, "Parse arbitrary r-type # one", "[id]")
 {
@@ -113,164 +113,164 @@ TEST_CASE_METHOD(IDFixture, "Parse arbitrary r-type # one", "[id]")
 	delete i;
 }
 
-// TEST_CASE_METHOD(IDFixture, "Parse arbitrary r-type # two", "[id]")
-// {
-// 	signed int t;
-// 	InstrDTO *i;
+TEST_CASE_METHOD(IDFixture, "Parse arbitrary r-type # two", "[id]")
+{
+	signed int t;
+	InstrDTO *i;
 
-// 	t = this->encode_R_type(0b10000, 0b01000, 0b00100, 0b10, 0b0);
-// 	i = this->decode_bits(t);
+	t = this->encode_R_type(0b10000, 0b01000, 0b00100, 0b10, 0b0);
+	i = this->decode_bits(t);
 
-// 	CHECK(i->get_s1() == 0x00000000); // registers are empty
-// 	CHECK(i->get_s2() == 0x00000000);
-// 	CHECK(i->get_s3() == 0x00000000);
-// 	CHECK(i->get_mnemonic() == SUB);
+	CHECK(i->get_s1() == 0x00000000); // registers are empty
+	CHECK(i->get_s2() == 0x00000000);
+	CHECK(i->get_s3() == 0x00000000);
+	CHECK(i->get_mnemonic() == SUB);
 
-// 	delete i;
-// }
+	delete i;
+}
 
-// TEST_CASE_METHOD(IDFixture, "Parse arbitrary i-type # one", "[id]")
-// {
-// 	signed int t;
-// 	InstrDTO *i;
+TEST_CASE_METHOD(IDFixture, "Parse arbitrary i-type # one", "[id]")
+{
+	signed int t;
+	InstrDTO *i;
 
-// 	t = this->encode_I_type(0xF, 0b1, 0b10, 0b0111, 0b1);
-// 	i = this->decode_bits(t);
+	t = this->encode_I_type(0xF, 0b1, 0b10, 0b0111, 0b1);
+	i = this->decode_bits(t);
 
-// 	CHECK(i->get_s1() == 0x00000000); // registers are empty
-// 	CHECK(i->get_s2() == 0x00000000);
-// 	CHECK(i->get_s3() == 0xF);
-// 	CHECK(i->get_mnemonic() == SFTLI);
+	CHECK(i->get_s1() == 0x00000000); // registers are empty
+	CHECK(i->get_s2() == 0x00000000);
+	CHECK(i->get_s3() == 0xF);
+	CHECK(i->get_mnemonic() == SFTLI);
 
-// 	delete i;
-// }
+	delete i;
+}
 
-// TEST_CASE_METHOD(IDFixture, "Parse arbitrary i-type # two", "[id]")
-// {
-// 	signed int t;
-// 	InstrDTO *i;
+TEST_CASE_METHOD(IDFixture, "Parse arbitrary i-type # two", "[id]")
+{
+	signed int t;
+	InstrDTO *i;
 
-// 	t = this->encode_I_type(0xCC, 0b010, 0b101, 0b1011, 0b1);
-// 	i = this->decode_bits(t);
+	t = this->encode_I_type(0xCC, 0b010, 0b101, 0b1011, 0b1);
+	i = this->decode_bits(t);
 	
-// 	CHECK(i->get_s1() == 0x00000000); // registers are empty
-// 	CHECK(i->get_s2() == 0x00000000);
-// 	CHECK(i->get_s3() == 0xCC);
-// 	CHECK(i->get_mnemonic() == STORE);
-
-// 	delete i;
-// }
-
-// TEST_CASE_METHOD(IDFixture, "Parse arbitrary j-type # one", "[id]")
-// {
-// 	signed int t;
-// 	InstrDTO *i;
-
-// 	t = this->encode_J_type(0x3456, 0b10101, 0b0111, 0b10);
-// 	i = this->decode_bits(t);
-
-// 	CHECK(i->get_s1() == 0x00000000); // registers are empty
-// 	CHECK(i->get_s2() == 0x3456);
-// 	CHECK(i->get_mnemonic() == BOF);
-
-// 	delete i;
-// }
-
-// TEST_CASE_METHOD(IDFixture, "Parse arbitrary j-type # two", "[id]")
-// {
-// 	signed int t;
-// 	InstrDTO *i;
-
-// 	t = this->encode_J_type(0xBBCCF, 0b10101, 0b0011, 0b10);
-// 	i = this->decode_bits(t);
-
-// 	CHECK(i->get_s1() == 0x00000000); // registers are empty
-// 	CHECK(i->get_s2() == 0xBBCCF);
-// 	CHECK(i->get_mnemonic() == JAL);
-
-// 	delete i;
-// }
-
-// TEST_CASE_METHOD(IDFixture, "read does not conflict with read", "[id]")
-// {
-// 	signed int v;
-// 	Response r;
-
-// 	v = 0b1;
-// 	r = this->d->read_guard(v);
-// 	CHECK(v == 0b0);
-// 	REQUIRE(r == OK);
-
-// 	v = 0b1;
-// 	this->d->read_guard(v);
-// 	REQUIRE(v == 0b0);
-// }
-
-// TEST_CASE_METHOD(IDFixture, "write does not conflict with write", "[id]")
-// {
-// 	signed int v;
-
-// 	v = 0b1;
-// 	this->d->write_guard(v);
-// 	REQUIRE(v == 0b0);
-
-// 	v = 0b1;
-// 	this->d->write_guard(v);
-// 	REQUIRE(v == 0b0);
-// }
-
-// TEST_CASE_METHOD(IDFixture, "write does not conflict with read", "[id]")
-// {
-// 	signed int v;
-// 	Response r;
-
-// 	v = 0b1;
-// 	r = this->d->read_guard(v);
-// 	CHECK(v == 0b0);
-// 	REQUIRE(r == OK);
-
-// 	v = 0b1;
-// 	this->d->write_guard(v);
-// 	REQUIRE(v == 0b0);
-// }
-
-// TEST_CASE_METHOD(IDFixture, "read does conflict with write", "[id]")
-// {
-// 	signed int v;
-// 	Response r;
-
-// 	v = 0b1;
-// 	this->d->write_guard(v);
-// 	REQUIRE(v == 0b0);
-
-// 	v = 0b1;
-// 	r = this->d->read_guard(v);
-// 	CHECK(v == 0b01);
-// 	REQUIRE(r == STALLED);
-// }
-
-// TEST_CASE_METHOD(IDFixture, "stores indefinite conflicts", "[id]")
-// {
-// 	signed int v, ov;
-// 	Response r;
-
-// 	v = 0b0;
-// 	ov = v;
-// 	while (v < 0b110) {
-// 		this->d->write_guard(v);
-// 		REQUIRE(v == 0b0);
-// 		v = ++ov;
-// 	}
-// 	this->d->write_guard(v);
-// 	REQUIRE(v == 0b0);
-
-// 	v = 0b110;
-// 	r = this->d->read_guard(v);
-// 	CHECK(v == 0b110);
-// 	REQUIRE(r == STALLED);
-
-// 	v = 0b0;
-// 	r = this->d->read_guard(v);
-// 	CHECK(v == 0b0);
-// 	REQUIRE(r == STALLED);
-// }
+	CHECK(i->get_s1() == 0x00000000); // registers are empty
+	CHECK(i->get_s2() == 0x00000000);
+	CHECK(i->get_s3() == 0xCC);
+	CHECK(i->get_mnemonic() == STORE);
+
+	delete i;
+}
+
+TEST_CASE_METHOD(IDFixture, "Parse arbitrary j-type # one", "[id]")
+{
+	signed int t;
+	InstrDTO *i;
+
+	t = this->encode_J_type(0x3456, 0b10101, 0b0111, 0b10);
+	i = this->decode_bits(t);
+
+	CHECK(i->get_s1() == 0x00000000); // registers are empty
+	CHECK(i->get_s2() == 0x3456);
+	CHECK(i->get_mnemonic() == BOF);
+
+	delete i;
+}
+
+TEST_CASE_METHOD(IDFixture, "Parse arbitrary j-type # two", "[id]")
+{
+	signed int t;
+	InstrDTO *i;
+
+	t = this->encode_J_type(0xBBCCF, 0b10101, 0b0011, 0b10);
+	i = this->decode_bits(t);
+
+	CHECK(i->get_s1() == 0x00000000); // registers are empty
+	CHECK(i->get_s2() == 0xBBCCF);
+	CHECK(i->get_mnemonic() == JAL);
+
+	delete i;
+}
+
+TEST_CASE_METHOD(IDFixture, "read does not conflict with read", "[id]")
+{
+	signed int v;
+	Response r;
+
+	v = 0b1;
+	r = this->d->read_guard(v);
+	CHECK(v == 0b0);
+	REQUIRE(r == OK);
+
+	v = 0b1;
+	this->d->read_guard(v);
+	REQUIRE(v == 0b0);
+}
+
+TEST_CASE_METHOD(IDFixture, "write does not conflict with write", "[id]")
+{
+	signed int v;
+
+	v = 0b1;
+	this->d->write_guard(v);
+	REQUIRE(v == 0b0);
+
+	v = 0b1;
+	this->d->write_guard(v);
+	REQUIRE(v == 0b0);
+}
+
+TEST_CASE_METHOD(IDFixture, "write does not conflict with read", "[id]")
+{
+	signed int v;
+	Response r;
+
+	v = 0b1;
+	r = this->d->read_guard(v);
+	CHECK(v == 0b0);
+	REQUIRE(r == OK);
+
+	v = 0b1;
+	this->d->write_guard(v);
+	REQUIRE(v == 0b0);
+}
+
+TEST_CASE_METHOD(IDFixture, "read does conflict with write", "[id]")
+{
+	signed int v;
+	Response r;
+
+	v = 0b1;
+	this->d->write_guard(v);
+	REQUIRE(v == 0b0);
+
+	v = 0b1;
+	r = this->d->read_guard(v);
+	CHECK(v == 0b01);
+	REQUIRE(r == STALLED);
+}
+
+TEST_CASE_METHOD(IDFixture, "stores indefinite conflicts", "[id]")
+{
+	signed int v, ov;
+	Response r;
+
+	v = 0b0;
+	ov = v;
+	while (v < 0b110) {
+		this->d->write_guard(v);
+		REQUIRE(v == 0b0);
+		v = ++ov;
+	}
+	this->d->write_guard(v);
+	REQUIRE(v == 0b0);
+
+	v = 0b110;
+	r = this->d->read_guard(v);
+	CHECK(v == 0b110);
+	REQUIRE(r == STALLED);
+
+	v = 0b0;
+	r = this->d->read_guard(v);
+	CHECK(v == 0b0);
+	REQUIRE(r == STALLED);
+}
-- 
cgit v1.2.3


From 68324683cde10c636a4a602644f3e64d24b0e412 Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Tue, 1 Apr 2025 20:36:31 -0400
Subject: Lots of fixes and tests

---
 inc/ex.h              |   2 +-
 inc/id.h              |   2 +-
 inc/instrDTO.h        |  15 ++-
 inc/stage.h           |  10 +-
 src/sim/controller.cc |   1 +
 src/sim/ex.cc         |  53 +++++++++--
 src/sim/id.cc         |  21 +++-
 src/sim/if.cc         |   1 +
 src/sim/instrDTO.cc   |   4 +
 src/sim/mm.cc         |   1 -
 src/sim/stage.cc      |   7 +-
 src/sim/wb.cc         |   1 +
 tests/controller.cc   | 259 +++++++++++++++++++++++++++++++++++++++++++++-----
 13 files changed, 331 insertions(+), 46 deletions(-)

(limited to 'tests/controller.cc')

diff --git a/inc/ex.h b/inc/ex.h
index 6d4254e..e4c9d2b 100644
--- a/inc/ex.h
+++ b/inc/ex.h
@@ -25,7 +25,7 @@ class EX : public Stage
 	 */
 	std::unordered_map<
 		Mnemonic,
-		std::function<void(signed int &s1, signed int s2, signed int s3)>>
+		std::function<void(signed int &s1, signed int s2, signed int s3, unsigned int pc)>>
 		instr_map;
 };
 
diff --git a/inc/id.h b/inc/id.h
index ebbe290..6178ad2 100644
--- a/inc/id.h
+++ b/inc/id.h
@@ -66,7 +66,7 @@ class ID : public Stage
 	 */
 	void get_instr_fields(signed int &s1, signed int &s2, signed int &s3, Mnemonic &m, Type &t);
 	void decode_R_type(signed int &s1, signed int &s2, signed int &s3);
-	void decode_I_type(signed int &s1, signed int &s2, signed int &s3);
+	void decode_I_type(signed int &s1, signed int &s2, signed int &s3, Mnemonic &m);
 	void decode_J_type(signed int &s1, signed int &s2);
 	/**
 	 * Helper for `get_instr_fields`.
diff --git a/inc/instrDTO.h b/inc/instrDTO.h
index 8249122..b6dec06 100644
--- a/inc/instrDTO.h
+++ b/inc/instrDTO.h
@@ -47,6 +47,10 @@ class InstrDTO
 	 * @return the type of the instruction
 	 */
 	Type get_type();
+	/**
+	 * @return the program counter at the time this instruction was fetched
+	 */
+	unsigned int get_pc();
 
 	/**
 	 * @param set hist key
@@ -72,11 +76,15 @@ class InstrDTO
 	 * @param the mnemonic of the instruction
 	 */
 	void set_mnemonic(Mnemonic);
-	
+
 	/**
 	 * @param the type of the instruction
 	 */
 	void set_type(Type);
+	/**
+	 * @param the program counter at the time this instruction was fetched
+	 */
+	void set_pc(unsigned int pc);
 
   private:
 	/**
@@ -100,11 +108,14 @@ class InstrDTO
 	 * The mnemonic of the operation.
 	 */
 	Mnemonic mnemonic;
-
 	/**
 	 * Type of the instruction
 	 */
 	Type type;
+	/**
+	 * The PC of the instruction
+	 */
+	unsigned int pc;
 };
 
 #endif /* INSTRDTO_H_INCLUDED */
diff --git a/inc/stage.h b/inc/stage.h
index 87ee9c1..20f0191 100644
--- a/inc/stage.h
+++ b/inc/stage.h
@@ -64,6 +64,11 @@ class Stage
 	 */
 	void squash();
 
+	/**
+	 * The set of registers currently checked out.
+	 */
+	static std::deque<signed int> checked_out;
+
   protected:
 	/**
 	 * The function expected to do the majority of the work.
@@ -120,11 +125,6 @@ class Stage
 	 * The current clock cycle.
 	 */
 	static int clock_cycle;
-	// TODO fix this comment after writeback stage
-	/**
-	 * The set of registers currently checked out.
-	 */
-	static std::deque<signed int> checked_out;
 	/**
 	 * A pointer to the next stage in the pipeline.
 	 */
diff --git a/src/sim/controller.cc b/src/sim/controller.cc
index 293ee73..0b5c4d0 100644
--- a/src/sim/controller.cc
+++ b/src/sim/controller.cc
@@ -34,6 +34,7 @@ InstrDTO *Controller::advance(Response p)
 	InstrDTO *r;
 	r = this->next->advance(p);
 	++this->clock_cycle;
+	
 	return r;
 }
 
diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index ec4c47f..98a2d19 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -9,7 +9,7 @@
 
 // clang-format off
 #define INIT_INSTRUCTION(mnemonic, body)					\
-	{mnemonic, [this](signed int &s1, signed int s2, signed int s3) { \
+	{mnemonic, [this](signed int &s1, signed int s2, signed int s3, unsigned int pc) {	\
 		body; \
 	}}
 // clang-format on
@@ -24,6 +24,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			ADD,
 			{
 				s1 = s1 + s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -32,6 +33,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			SUB,
 			{
 				s1 = s1 - s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -40,6 +42,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			MUL,
 			{
 				s1 = s1 * s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -48,6 +51,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			QUOT,
 			{
 				s1 = s1 / s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -56,6 +60,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			REM,
 			{
 				s1 = s1 % s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -64,6 +69,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			SFTR,
 			{
 				s1 = s1 >> s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -72,6 +78,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			SFTL,
 			{
 				s1 = s1 << s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -80,6 +87,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			AND,
 			{
 				s1 = s1 & s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -88,6 +96,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			OR,
 			{
 				s1 = s1 | s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -96,6 +105,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			NOT,
 			{
 				s1 = ~s1;
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)this;
@@ -105,6 +115,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			XOR,
 			{
 				s1 = s1 ^ s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -112,6 +123,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			ADDV,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -121,6 +133,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			SUBV,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -130,6 +143,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			MULV,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -139,6 +153,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			DIVV,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -148,16 +163,19 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			CMP,
 			{
+				cout << "CMP: " << s1 << ":" << s2 << std::endl;
 				(s1 > s2) ? this->set_condition(GT, true)
 						  : this->set_condition(GT, false);
 				(s1 == s2) ? this->set_condition(EQ, true)
 						   : this->set_condition(EQ, false);
+				(void)pc;
 				(void)s3;
 			}),
 
 		INIT_INSTRUCTION(
 			CEV,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -169,6 +187,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			LOAD,
 			{
 				s1 = s1 + s3;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -176,6 +195,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			LOADV,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -185,8 +205,10 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			ADDI,
 			{
+				std::cout << this->id << ": " << s1 << "," << s2 << "," << s3
+						  << std::endl;
 				s1 = s1 + s3;
-				std::cout << "= " << s2 << std::endl;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -195,6 +217,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			SUBI,
 			{
 				s1 = s1 - s3;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -203,6 +226,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			SFTRI,
 			{
 				s1 = s1 >> s3;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -211,6 +235,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			SFTLI,
 			{
 				s1 = s1 << s3;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -219,6 +244,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			ANDI,
 			{
 				s1 = s1 & s3;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -227,6 +253,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			ORI,
 			{
 				s1 = s1 | s3;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -235,6 +262,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			XORI,
 			{
 				s1 = s1 ^ s3;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -243,6 +271,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			STORE,
 			{
 				s1 = s1 + s3;
+				(void)pc;
 				(void)s2;
 				(void)this;
 			}),
@@ -250,6 +279,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			STOREV,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -261,6 +291,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			JMP,
 			{
 				s1 = s1 + s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -268,7 +299,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			JRL,
 			{
-				s1 = this->pc + s2;
+				s1 = pc + s2;
 				(void)s3;
 				(void)this;
 			}),
@@ -277,6 +308,7 @@ EX::EX(Stage *stage) : Stage(stage)
 			JAL,
 			{
 				s1 = s1 + s2;
+				(void)pc;
 				(void)s3;
 				(void)this;
 			}),
@@ -284,7 +316,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			BEQ,
 			{
-				(this->get_condition(EQ)) ? s1 = wrap_address(this->pc + s2)
+				(this->get_condition(EQ)) ? s1 = wrap_address(pc + s2)
 										  : s1 = -1;
 				(void)s3;
 			}),
@@ -292,7 +324,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			BGT,
 			{
-				(this->get_condition(GT)) ? s1 = wrap_address(this->pc + s2)
+				(this->get_condition(GT)) ? s1 = wrap_address(pc + s2)
 										  : s1 = -1;
 				(void)s3;
 			}),
@@ -300,7 +332,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			BUF,
 			{
-				(this->get_condition(UF)) ? s1 = wrap_address(this->pc) + s2
+				(this->get_condition(UF)) ? s1 = wrap_address(pc + s2)
 										  : s1 = -1;
 				(void)s3;
 			}),
@@ -308,7 +340,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			BOF,
 			{
-				(this->get_condition(OF)) ? s1 = wrap_address(this->pc + s2)
+				(this->get_condition(OF)) ? s1 = wrap_address(pc + s2)
 										  : s1 = -1;
 				(void)s3;
 			}),
@@ -316,6 +348,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			PUSH,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -325,6 +358,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			POP,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -335,6 +369,7 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			NOP,
 			{
+				(void)pc;
 				(void)s3;
 				(void)s2;
 				(void)s1;
@@ -346,14 +381,16 @@ EX::EX(Stage *stage) : Stage(stage)
 void EX::advance_helper()
 {
 	signed int s1, s2, s3;
+	unsigned int pc;
 	Mnemonic m;
 
 	m = this->curr_instr->get_mnemonic();
 	s1 = this->curr_instr->get_s1();
 	s2 = this->curr_instr->get_s2();
 	s3 = this->curr_instr->get_s3();
+	pc = this->curr_instr->get_pc();
 
-	this->instr_map[m](s1, s2, s3);
+	this->instr_map[m](s1, s2, s3, pc );
 
 	this->curr_instr->set_s1(s1);
 	this->status = OK;
diff --git a/src/sim/id.cc b/src/sim/id.cc
index ddac35b..805a4df 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -51,6 +51,9 @@ void ID::advance_helper()
 	if (curr_instr->get_mnemonic() == NOP)
 		this->status = OK;
 	else {
+		std::cout << this->id << ": " << this->curr_instr->get_s1() << ","
+				  << this->curr_instr->get_s2() << ","
+				  << this->curr_instr->get_s3() << std::endl;
 		s1 = curr_instr->get_instr_bits();
 		get_instr_fields(s1, s2, s3, m, t);
 		if (this->status == OK) {
@@ -60,6 +63,9 @@ void ID::advance_helper()
 			curr_instr->set_mnemonic(m);
 			curr_instr->set_type(t);
 		}
+		std::cout << this->id << ": " << this->curr_instr->get_s1() << ","
+				  << this->curr_instr->get_s2() << ","
+				  << this->curr_instr->get_s3() << std::endl;
 	}
 }
 
@@ -76,7 +82,7 @@ void ID::get_instr_fields(
 		break;
 	case 0b01:
 		t = I;
-		this->decode_I_type(s1, s2, s3);
+		this->decode_I_type(s1, s2, s3, m);
 		break;
 	case 0b10:
 		t = J;
@@ -107,9 +113,11 @@ void ID::decode_R_type(signed int &s1, signed int &s2, signed int &s3)
 	this->status = (r1 == OK && r2 == OK) ? OK : STALLED;
 }
 
-void ID::decode_I_type(signed int &s1, signed int &s2, signed int &s3)
+void ID::decode_I_type(
+	signed int &s1, signed int &s2, signed int &s3, Mnemonic &m)
 {
 	unsigned int s0b, s1b, s2b;
+	Response r1;
 
 	s0b = REG_SIZE;
 	s1b = s0b + REG_SIZE;
@@ -118,8 +126,13 @@ void ID::decode_I_type(signed int &s1, signed int &s2, signed int &s3)
 	s2 = GET_MID_BITS(s1, s0b, s1b);
 	s1 = GET_LS_BITS(s1, s0b);
 
-	this->status = this->read_guard(s1);
-	this->write_guard(s2);
+	std::cout << m << ":" << s2 << std::endl;
+	r1 = this->read_guard(s1);
+	if (m != STORE && m != STOREV) {
+		this->status = r1;
+		this->write_guard(s2);
+	} else
+		this->status = (this->read_guard(s2) == OK && r1 == OK) ? OK : STALLED;
 }
 
 void ID::decode_J_type(signed int &s1, signed int &s2)
diff --git a/src/sim/if.cc b/src/sim/if.cc
index bc40688..85fb27f 100644
--- a/src/sim/if.cc
+++ b/src/sim/if.cc
@@ -33,6 +33,7 @@ void IF::advance_helper()
 		if (r == OK) {
 			this->curr_instr = new InstrDTO();
 			this->curr_instr->set_instr_bits(bits);
+			this->curr_instr->set_pc(this->pc);
 		}
 	}
 }
diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc
index 7324ba9..d36e957 100644
--- a/src/sim/instrDTO.cc
+++ b/src/sim/instrDTO.cc
@@ -25,6 +25,8 @@ Mnemonic InstrDTO::get_mnemonic() { return this->mnemonic; }
 
 Type InstrDTO::get_type() { return this->type; }
 
+unsigned int InstrDTO::get_pc() { return this->pc; }
+
 void InstrDTO::set_time_of(Accessor a, int i) { this->hist[a] = i; }
 
 void InstrDTO::set_instr_bits(signed int instr) { this->instr_bits = instr; }
@@ -38,3 +40,5 @@ void InstrDTO::set_s3(signed int s) { this->s3 = s; }
 void InstrDTO::set_mnemonic(Mnemonic m) { this->mnemonic = m; }
 
 void InstrDTO::set_type(Type t) { this->type = t; }
+
+void InstrDTO::set_pc(unsigned int pc) { this->pc = pc; }
diff --git a/src/sim/mm.cc b/src/sim/mm.cc
index e29bf90..c83ae7d 100644
--- a/src/sim/mm.cc
+++ b/src/sim/mm.cc
@@ -10,7 +10,6 @@ void MM::advance_helper()
 {
 	signed int data;
 
-	std::cout << "mem" << this->curr_instr->get_s2() << std::endl;
 	switch (this->curr_instr->get_mnemonic()) {
 	case LOAD:
 		this->status = this->storage->read_word(
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index b10a206..bd0ff6b 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -95,8 +95,11 @@ bool Stage::is_checked_out(signed int r)
 
 void Stage::squash()
 {
-	this->curr_instr->set_mnemonic(NOP);
-	this->status = OK;
+	if (curr_instr) {
+		std::cout << "!!!" << std::endl;
+		this->curr_instr->set_mnemonic(NOP);
+		this->status = OK;
+	}
 	if (this->next) {
 		this->next->squash();
 	}
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 01768e8..50acd05 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -28,6 +28,7 @@ void WB::write_handler()
 
 	reg = this->checked_out.front();
 	this->checked_out.pop_front();
+	std::cout << "storing " << reg << " with " << this->curr_instr->get_s1() << std::endl;
 	this->store_register(reg, this->curr_instr->get_s1());
 }
 
diff --git a/tests/controller.cc b/tests/controller.cc
index f2ef3de..c36eba6 100644
--- a/tests/controller.cc
+++ b/tests/controller.cc
@@ -65,25 +65,42 @@ TEST_CASE_METHOD(
 
 TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 {
-	signed int b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11;
+	signed int b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14,
+		b15;
 	std::vector<signed int> p;
 	InstrDTO *i;
 
 	// I-TYPE              /    /    /   /
-	b0 = 0b00000010000000000001000000001101; // ADDI $sp $0 0x200;
+	b0 = 0b00000010000000000001000000001101; // ADDI $2 $0 0x200;
 	b1 = 0b00000000000000010010100000001101; // ADDI $5 $0 0x1;
-	b2 = 0b00000000000000000001000101101101; // STORE $5 0($sp);  (RAW HAZARD)!
+	b2 = 0b00000000000000000010100010101101; // STORE $5 0($2);  (RAW HAZARD w
+											 // 1)!
 	// I-TYPE              /    /    /   /
 	b3 = 0b00000000000000100010100000001101; // ADDI $5 $0 0x2;   (RAW HAZARD)!
-	b4 = 0b00000000000000010001000101101101; // STORE $5 1($sp);  (RAW HAZARD)!
-	// // I-TYPE              /    /    /   /
-	// b9 = 0b00000000000000000010100000001101;  // ADDI $5 $0 0x0;
-	// // I-TYPE               /    /    /   /
-	// b10 = 0b00000000000000110011000000001101; // ADDI $6 $0 0x3;
-	// // J-TYPE                    /    /   /
-	// b11 = 0b00000000000000000011100000001010; // jrl CHECK
-
-	p = {b0, b1, b2, b3};
+	b4 = 0b00000000000000010010100010101101; // STORE $5 1($2);  (RAW HAZARD)!
+	// // I-TYPE           /    /    /   /
+	b5 = 0b00000000000000000010100000001101; // ADDI $5 $0 0x0;
+	// // I-TYPE           /    /    /   /
+	b6 = 0b00000000000000010011000000001101; // ADDI $6 $0 0x1;
+	// // J-TYPE                /    /   /
+	b7 = 0b00000000000000000011100000001010; // JRL CHECK
+	// // R-TYPE     /    /    /    /    /
+	b8 = 0b00000000000100100101000100000100; // ADD $9 $2 $5;
+	// // I-TYPE           /    /    /   /
+	b9 = 0b00000000000000000011101001000101; // LOAD $7 0($9); (RAW HAZARD)!
+	//  // I-TYPE           /    /    /   /
+	b10 = 0b00000000000000010100001001000101; // LOAD $8 1($9);
+	//  // R-TYPE     /    /    /    /    /
+	b11 = 0b00000000000011101000001110000100; // ADD $7 $7 $8;
+	// I-TYPE               /    /    /   /
+	b12 = 0b00000000000000000011101001101101; // STORE $7 0($9);
+	b13 = 0b00000010000000010010100101001101; // ADDI $5 $5 0x1;
+	//  // R-TYPE     /    /    /    /    /
+	b14 = 0b00000000000111100101001101000000; // CMP $6 $5
+	//  // J-TYPE                /    /   /
+	b15 = 0b11111111111111111100100000010110; // bgt LOOP
+
+	p = {b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15};
 	this->d->load(p);
 
 	this->fill_pipe();
@@ -101,6 +118,7 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 	CHECK(this->ct->get_gprs().at(2) == 0x200);
 	CHECK(i->get_mnemonic() == ADDI);
 	CHECK(i->get_instr_bits() == b0);
+	CHECK(this->ct->checked_out.front() == 0x5);
 
 	delete i;
 	i = this->ct->advance(WAIT);
@@ -128,21 +146,28 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
 	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
 	REQUIRE(i != nullptr);
 
 	CHECK(i->get_time_of(FETCH) == 5);
-	CHECK(i->get_time_of(DCDE) == 8); // the previous conflicting instruction wrote here!
+	CHECK(
+		i->get_time_of(DCDE) ==
+		8); // the previous conflicting instruction wrote here!
 	CHECK(i->get_time_of(EXEC) == 9);
-	CHECK(i->get_time_of(MEM) == 12); // waited for fetch + 2 dram
-	CHECK(i->get_time_of(WRITE) == 13);
-	CHECK(i->get_s1() == 0x1);
-	CHECK(i->get_s2() == 0x200);
+	CHECK(i->get_time_of(MEM) == 14); // waited for fetch + 3 dram
+	CHECK(i->get_time_of(WRITE) == 15);
+	CHECK(i->get_s1() == 0x200);
+	CHECK(i->get_s2() == 0x1);
 	CHECK(i->get_s3() == 0x0);
 	// NO STORE
 	CHECK(this->ct->get_gprs().at(2) == 0x200);
 	CHECK(this->ct->get_gprs().at(5) == 0x1);
 	CHECK(i->get_mnemonic() == STORE);
 	CHECK(i->get_instr_bits() == b2);
+	CHECK(this->ct->checked_out.front() == 0x5);
 
 	delete i;
 	i = this->ct->advance(WAIT);
@@ -150,16 +175,206 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 
 	CHECK(i->get_time_of(FETCH) == 8);
 	CHECK(i->get_time_of(DCDE) == 9);
-	CHECK(i->get_time_of(EXEC) == 12);
-	CHECK(i->get_time_of(MEM) == 13);
-	CHECK(i->get_time_of(WRITE) == 14);
+	CHECK(i->get_time_of(EXEC) == 14);
+	CHECK(i->get_time_of(MEM) == 15);
+	CHECK(i->get_time_of(WRITE) == 16);
 	CHECK(i->get_s1() == 0x2);
-	CHECK(i->get_s2() == 0x0);
+	CHECK(i->get_s2() == 0x1); // the previous value in the destination register
 	CHECK(i->get_s3() == 0x2);
-	// NO STORE
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
 	CHECK(this->ct->get_gprs().at(5) == 0x2);
 	CHECK(i->get_mnemonic() == ADDI);
 	CHECK(i->get_instr_bits() == b3);
 
 	delete i;
+
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 14); // fetching new line + mem
+	CHECK(
+		i->get_time_of(DCDE) ==
+		16); // the previous conflicting instruction wrote here!
+	CHECK(i->get_time_of(EXEC) == 17);
+	CHECK(i->get_time_of(MEM) == 18);
+	CHECK(i->get_time_of(WRITE) == 19);
+	CHECK(i->get_s1() == 0x201);
+	CHECK(i->get_s2() == 0x2); // address
+	CHECK(i->get_s3() == 0x1); // offset
+	// NO STORE
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(5) == 0x2);
+	CHECK(i->get_mnemonic() == STORE);
+	CHECK(i->get_instr_bits() == b4);
+	// CHECK(this->ct->checked_out.front() == 0x5);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 16);
+	CHECK(i->get_time_of(DCDE) == 17);
+	CHECK(i->get_time_of(EXEC) == 18);
+	CHECK(i->get_time_of(MEM) == 19);
+	CHECK(i->get_time_of(WRITE) == 20);
+	CHECK(i->get_s1() == 0x0);
+	CHECK(i->get_s2() == 0x2);
+	CHECK(i->get_s3() == 0x0);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(5) == 0x0);
+	CHECK(i->get_mnemonic() == ADDI);
+	CHECK(i->get_instr_bits() == b5);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 17);
+	CHECK(i->get_time_of(DCDE) == 18);
+	CHECK(i->get_time_of(EXEC) == 19);
+	CHECK(i->get_time_of(MEM) == 20);
+	CHECK(i->get_time_of(WRITE) == 21);
+	CHECK(i->get_s1() == 0x1);
+	CHECK(i->get_s2() == 0x0);
+	CHECK(i->get_s3() == 0x1);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(i->get_pc() == 0x6);
+	CHECK(this->ct->get_pc() == 0x9);
+	CHECK(i->get_mnemonic() == ADDI);
+	CHECK(i->get_instr_bits() == b6);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 18);
+	CHECK(i->get_time_of(DCDE) == 19);
+	CHECK(i->get_time_of(EXEC) == 20);
+	CHECK(i->get_time_of(MEM) == 21);
+	CHECK(i->get_time_of(WRITE) == 22);
+	CHECK(i->get_s1() == 0xE);
+	CHECK(i->get_s2() == 0x7);
+	CHECK(i->get_s3() == 0x0); // doesn't exist
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(i->get_pc() == 0x7);
+	CHECK(this->ct->get_pc() == 0xE);
+	CHECK(i->get_mnemonic() == JRL);
+	CHECK(i->get_instr_bits() == b7);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr); // switching cache lines in fetch
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_mnemonic() == NOP); // squashed
+
+	delete i;
+	i = this->ct->advance(WAIT); // nops?
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(
+		i->get_time_of(FETCH) ==
+		24); // 6 greater than last fetch (4 flush pipe, 2 dram)
+	CHECK(i->get_time_of(DCDE) == 25);
+	CHECK(i->get_time_of(EXEC) == 26);
+	CHECK(i->get_time_of(MEM) == 27);
+	CHECK(i->get_time_of(WRITE) == 28);
+	CHECK(i->get_s1() == 0x1);
+	CHECK(i->get_s2() == 0x0);
+	CHECK(i->get_s3() == 0x0);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(5) == 0x0);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(this->ct->get_condition(GT) == true);
+	CHECK(this->ct->get_condition(EQ) == false);
+	CHECK(i->get_mnemonic() == CMP);
+	CHECK(i->get_instr_bits() == b14);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 25);
+	CHECK(i->get_time_of(DCDE) == 26);
+	CHECK(i->get_time_of(EXEC) == 27);
+	CHECK(i->get_time_of(MEM) == 28);
+	CHECK(i->get_time_of(WRITE) == 29);
+	CHECK(i->get_s1() == 0x8);
+	CHECK(i->get_s2() == 0b111111111111111111001);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(5) == 0x0);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(this->ct->get_condition(GT) == true);
+	CHECK(this->ct->get_condition(EQ) == false);
+	CHECK(this->ct->get_pc() == 0x9);
+	CHECK(i->get_mnemonic() == BGT);
+	CHECK(i->get_instr_bits() == b15);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_mnemonic() == NOP);
+	delete i;
+	
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr); // it was already in cache
+	
+	CHECK(i->get_time_of(FETCH) == 29); // clear out pipe (4)
+	CHECK(i->get_time_of(DCDE) == 30);
+	CHECK(i->get_time_of(EXEC) == 31);
+	CHECK(i->get_time_of(MEM) == 32);
+	CHECK(i->get_time_of(WRITE) == 33);
+	CHECK(i->get_s1() == 0x200);
+	CHECK(i->get_s2() == 0x0);
+	CHECK(i->get_s3() == 0x0);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(this->ct->get_gprs().at(9) == 0x200);
+	CHECK(i->get_pc() == 0x8);
+	CHECK(this->ct->get_pc() == 0xB);
+	CHECK(i->get_mnemonic() == ADD);
+	CHECK(i->get_instr_bits() == b8);
+
+	delete i;
+	i = this->ct->advance(WAIT); // RAW
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 30);
+	CHECK(i->get_time_of(DCDE) == 33);
+	CHECK(i->get_time_of(EXEC) == 34);
+	CHECK(i->get_time_of(MEM) == 35);
+	CHECK(i->get_time_of(WRITE) == 36);
+	CHECK(i->get_s1() == 0x0);
+	CHECK(i->get_s2() == 0x200);
+	CHECK(i->get_s3() == 0x0);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(this->ct->get_gprs().at(7) == 0x1);
+	CHECK(this->ct->get_gprs().at(9) == 0x200);
+	CHECK(i->get_mnemonic() == LOAD);
+	CHECK(i->get_instr_bits() == b9);
+
+	delete i;
 }
-- 
cgit v1.2.3


From d4e3a7a3b1cff6885978093d5cc125e38cc397b3 Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Tue, 1 Apr 2025 22:06:42 -0400
Subject: Finish adding initial tests for full pipeline

---
 inc/id.h            |  2 +-
 inc/stage.h         |  5 -----
 src/sim/ex.cc       |  3 ---
 src/sim/id.cc       | 12 +++---------
 src/sim/instrDTO.cc |  1 +
 src/sim/mm.cc       |  2 +-
 src/sim/stage.cc    |  3 ---
 src/sim/wb.cc       |  1 -
 tests/controller.cc | 10 ++++------
 tests/ex.cc         | 39 +++++++++++++++------------------------
 10 files changed, 25 insertions(+), 53 deletions(-)

(limited to 'tests/controller.cc')

diff --git a/inc/id.h b/inc/id.h
index 6178ad2..fd8c874 100644
--- a/inc/id.h
+++ b/inc/id.h
@@ -67,7 +67,7 @@ class ID : public Stage
 	void get_instr_fields(signed int &s1, signed int &s2, signed int &s3, Mnemonic &m, Type &t);
 	void decode_R_type(signed int &s1, signed int &s2, signed int &s3);
 	void decode_I_type(signed int &s1, signed int &s2, signed int &s3, Mnemonic &m);
-	void decode_J_type(signed int &s1, signed int &s2);
+	void decode_J_type(signed int &s1, signed int &s2, signed int &s3);
 	/**
 	 * Helper for `get_instr_fields`.
 	 * Given a raw instruction, returns the mnemonic and type.
diff --git a/inc/stage.h b/inc/stage.h
index 20f0191..51ab667 100644
--- a/inc/stage.h
+++ b/inc/stage.h
@@ -54,11 +54,6 @@ class Stage
 	 */
 	void set_condition(CC c, bool v);
 
-	/**
-	 * Sets the value of the PC register.
-	 */
-	void set_pc(unsigned int pc);
-
 	/**
 	 * Squashes the pipeline.
 	 */
diff --git a/src/sim/ex.cc b/src/sim/ex.cc
index 98a2d19..b6f8a1d 100644
--- a/src/sim/ex.cc
+++ b/src/sim/ex.cc
@@ -163,7 +163,6 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			CMP,
 			{
-				cout << "CMP: " << s1 << ":" << s2 << std::endl;
 				(s1 > s2) ? this->set_condition(GT, true)
 						  : this->set_condition(GT, false);
 				(s1 == s2) ? this->set_condition(EQ, true)
@@ -205,8 +204,6 @@ EX::EX(Stage *stage) : Stage(stage)
 		INIT_INSTRUCTION(
 			ADDI,
 			{
-				std::cout << this->id << ": " << s1 << "," << s2 << "," << s3
-						  << std::endl;
 				s1 = s1 + s3;
 				(void)pc;
 				(void)s2;
diff --git a/src/sim/id.cc b/src/sim/id.cc
index 805a4df..0df26f4 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -51,9 +51,6 @@ void ID::advance_helper()
 	if (curr_instr->get_mnemonic() == NOP)
 		this->status = OK;
 	else {
-		std::cout << this->id << ": " << this->curr_instr->get_s1() << ","
-				  << this->curr_instr->get_s2() << ","
-				  << this->curr_instr->get_s3() << std::endl;
 		s1 = curr_instr->get_instr_bits();
 		get_instr_fields(s1, s2, s3, m, t);
 		if (this->status == OK) {
@@ -63,9 +60,6 @@ void ID::advance_helper()
 			curr_instr->set_mnemonic(m);
 			curr_instr->set_type(t);
 		}
-		std::cout << this->id << ": " << this->curr_instr->get_s1() << ","
-				  << this->curr_instr->get_s2() << ","
-				  << this->curr_instr->get_s3() << std::endl;
 	}
 }
 
@@ -86,7 +80,7 @@ void ID::get_instr_fields(
 		break;
 	case 0b10:
 		t = J;
-		this->decode_J_type(s1, s2);
+		this->decode_J_type(s1, s2, s3);
 		break;
 	case 0b11:
 		t = INV;
@@ -126,7 +120,6 @@ void ID::decode_I_type(
 	s2 = GET_MID_BITS(s1, s0b, s1b);
 	s1 = GET_LS_BITS(s1, s0b);
 
-	std::cout << m << ":" << s2 << std::endl;
 	r1 = this->read_guard(s1);
 	if (m != STORE && m != STOREV) {
 		this->status = r1;
@@ -135,12 +128,13 @@ void ID::decode_I_type(
 		this->status = (this->read_guard(s2) == OK && r1 == OK) ? OK : STALLED;
 }
 
-void ID::decode_J_type(signed int &s1, signed int &s2)
+void ID::decode_J_type(signed int &s1, signed int &s2, signed int &s3)
 {
 	unsigned int s0b, s1b;
 
 	s0b = REG_SIZE;
 	s1b = WORD_SPEC;
+	s3 = 0;
 	s2 = GET_MID_BITS(s1, s0b, s1b);
 	s1 = GET_LS_BITS(s1, s0b);
 
diff --git a/src/sim/instrDTO.cc b/src/sim/instrDTO.cc
index d36e957..aa49b7e 100644
--- a/src/sim/instrDTO.cc
+++ b/src/sim/instrDTO.cc
@@ -9,6 +9,7 @@ InstrDTO::InstrDTO()
 	this->s3 = 0;
 	this->mnemonic = ADD;
 	this->type = INV;
+	this->pc = 0;
 }
 
 int InstrDTO::get_time_of(Accessor a) { return this->hist[a]; }
diff --git a/src/sim/mm.cc b/src/sim/mm.cc
index c83ae7d..07a362b 100644
--- a/src/sim/mm.cc
+++ b/src/sim/mm.cc
@@ -15,7 +15,7 @@ void MM::advance_helper()
 		this->status = this->storage->read_word(
 			this->id, this->curr_instr->get_s1(), data);
 		if (this->status == OK) {
-			this->curr_instr->set_s2(data);
+			this->curr_instr->set_s1(data);
 		} else
 			this->status = STALLED;
 		break;
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index bd0ff6b..24bdf75 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -22,8 +22,6 @@ int Stage::clock_cycle;
 
 bool Stage::get_condition(CC c) { return (this->gprs[3] >> c) & 1; }
 
-void Stage::set_pc(unsigned int pc) { this->pc = pc; }
-
 InstrDTO *Stage::advance(Response p)
 {
 	InstrDTO *r = nullptr;
@@ -96,7 +94,6 @@ bool Stage::is_checked_out(signed int r)
 void Stage::squash()
 {
 	if (curr_instr) {
-		std::cout << "!!!" << std::endl;
 		this->curr_instr->set_mnemonic(NOP);
 		this->status = OK;
 	}
diff --git a/src/sim/wb.cc b/src/sim/wb.cc
index 50acd05..01768e8 100644
--- a/src/sim/wb.cc
+++ b/src/sim/wb.cc
@@ -28,7 +28,6 @@ void WB::write_handler()
 
 	reg = this->checked_out.front();
 	this->checked_out.pop_front();
-	std::cout << "storing " << reg << " with " << this->curr_instr->get_s1() << std::endl;
 	this->store_register(reg, this->curr_instr->get_s1());
 }
 
diff --git a/tests/controller.cc b/tests/controller.cc
index c36eba6..c7e3c93 100644
--- a/tests/controller.cc
+++ b/tests/controller.cc
@@ -187,7 +187,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 	CHECK(i->get_instr_bits() == b3);
 
 	delete i;
-
 	i = this->ct->advance(WAIT);
 	REQUIRE(i == nullptr);
 	i = this->ct->advance(WAIT);
@@ -259,7 +258,6 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 	CHECK(i->get_time_of(WRITE) == 22);
 	CHECK(i->get_s1() == 0xE);
 	CHECK(i->get_s2() == 0x7);
-	CHECK(i->get_s3() == 0x0); // doesn't exist
 	CHECK(this->ct->get_gprs().at(2) == 0x200);
 	CHECK(this->ct->get_gprs().at(6) == 0x1);
 	CHECK(i->get_pc() == 0x7);
@@ -332,11 +330,11 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 	REQUIRE(i != nullptr);
 
 	CHECK(i->get_mnemonic() == NOP);
+
 	delete i;
-	
 	i = this->ct->advance(WAIT);
 	REQUIRE(i != nullptr); // it was already in cache
-	
+
 	CHECK(i->get_time_of(FETCH) == 29); // clear out pipe (4)
 	CHECK(i->get_time_of(DCDE) == 30);
 	CHECK(i->get_time_of(EXEC) == 31);
@@ -366,8 +364,8 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 	CHECK(i->get_time_of(EXEC) == 34);
 	CHECK(i->get_time_of(MEM) == 35);
 	CHECK(i->get_time_of(WRITE) == 36);
-	CHECK(i->get_s1() == 0x0);
-	CHECK(i->get_s2() == 0x200);
+	CHECK(i->get_s1() == 0x1);
+	CHECK(i->get_s2() == 0x0);
 	CHECK(i->get_s3() == 0x0);
 	CHECK(this->ct->get_gprs().at(2) == 0x200);
 	CHECK(this->ct->get_gprs().at(6) == 0x1);
diff --git a/tests/ex.cc b/tests/ex.cc
index a0af6fe..13437f7 100644
--- a/tests/ex.cc
+++ b/tests/ex.cc
@@ -640,8 +640,7 @@ TEST_CASE_METHOD(EXFixture, "JRL", "[ex]")
 	InstrDTO *i;
 
 	m = JRL;
-	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
+	s1 = 100, s2 = 69, s3 = 0;
 	i = execute_instr(s1, s2, s3, m);
 
 	CHECK(i->get_s1() == 69);
@@ -675,11 +674,10 @@ TEST_CASE_METHOD(EXFixture, "BEQ no cond", "[ex]")
 	InstrDTO *i;
 
 	m = BEQ;
-	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
+	s1 = 100, s2 = 50, s3 = 0;
 	i = execute_instr(s1, s2, s3, m);
 
-	CHECK(i->get_s1() == 42096);
+	CHECK(i->get_s1() == -1);
 
 	delete i;
 }
@@ -691,12 +689,11 @@ TEST_CASE_METHOD(EXFixture, "BEQ", "[ex]")
 	InstrDTO *i;
 
 	m = BEQ;
-	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
+	s1 = 100, s2 = 50, s3 = 0;
 	this->ct->set_condition(EQ, true);
 	i = execute_instr(s1, s2, s3, m);
 
-	CHECK(i->get_s1() == 69);
+	CHECK(i->get_s1() == 50);
 
 	delete i;
 }
@@ -708,11 +705,10 @@ TEST_CASE_METHOD(EXFixture, "BGT no cond", "[ex]")
 	InstrDTO *i;
 
 	m = BGT;
-	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
+	s1 = 100, s2 = 50, s3 = 0;
 	i = execute_instr(s1, s2, s3, m);
 
-	CHECK(i->get_s1() == 42096);
+	CHECK(i->get_s1() == -1);
 
 	delete i;
 }
@@ -724,12 +720,11 @@ TEST_CASE_METHOD(EXFixture, "BGT", "[ex]")
 	InstrDTO *i;
 
 	m = BGT;
-	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
+	s1 = 100, s2 = 50, s3 = 0;
 	this->ct->set_condition(GT, true);
 	i = execute_instr(s1, s2, s3, m);
 
-	CHECK(i->get_s1() == 69);
+	CHECK(i->get_s1() == 50);
 
 	delete i;
 }
@@ -742,10 +737,9 @@ TEST_CASE_METHOD(EXFixture, "BUF no cond", "[ex]")
 
 	m = BUF;
 	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
 	i = execute_instr(s1, s2, s3, m);
 
-	CHECK(i->get_s1() == 42096);
+	CHECK(i->get_s1() == -1);
 
 	delete i;
 }
@@ -757,12 +751,11 @@ TEST_CASE_METHOD(EXFixture, "BUF", "[ex]")
 	InstrDTO *i;
 
 	m = BUF;
-	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
+	s1 = 100, s2 = 50, s3 = 0;
 	this->ct->set_condition(UF, true);
 	i = execute_instr(s1, s2, s3, m);
 
-	CHECK(i->get_s1() == 69);
+	CHECK(i->get_s1() == 50);
 
 	delete i;
 }
@@ -775,10 +768,9 @@ TEST_CASE_METHOD(EXFixture, "BOF no cond", "[ex]")
 
 	m = BOF;
 	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
 	i = execute_instr(s1, s2, s3, m);
 
-	CHECK(i->get_s1() == 42096);
+	CHECK(i->get_s1() == -1);
 
 	delete i;
 }
@@ -790,12 +782,11 @@ TEST_CASE_METHOD(EXFixture, "BOF", "[ex]")
 	InstrDTO *i;
 
 	m = BOF;
-	s1 = 100, s2 = -42027, s3 = 0;
-	this->ct->set_pc(42096);
+	s1 = 100, s2 = 50, s3 = 0;
 	this->ct->set_condition(OF, true);
 	i = execute_instr(s1, s2, s3, m);
 
-	CHECK(i->get_s1() == 69);
+	CHECK(i->get_s1() == 50);
 
 	delete i;
 }
-- 
cgit v1.2.3


From 9e30d0054e7b3eb10e4e464b12ae3cc1eecc9585 Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Tue, 1 Apr 2025 23:22:12 -0400
Subject: Fix bug with decode pushing checked_out when delayed with RAW

---
 gui/gui.cc            |   6 +--
 gui/worker.cc         | 132 ++++++++++++++++++++++++++++++++------------------
 src/sim/controller.cc |   4 +-
 src/sim/id.cc         |   8 +--
 src/sim/stage.cc      |   6 +++
 tests/controller.cc   |  71 +++++++++++++++++++++++++++
 6 files changed, 172 insertions(+), 55 deletions(-)

(limited to 'tests/controller.cc')

diff --git a/gui/gui.cc b/gui/gui.cc
index b96d65d..3d3c56f 100644
--- a/gui/gui.cc
+++ b/gui/gui.cc
@@ -63,7 +63,7 @@ void displayArrayHTML(QTextEdit *textEdit, const std::array<int, GPR_NUM> &data)
     QString tableText = "<table border='1' cellspacing='0' cellpadding='8' style='border-collapse: collapse; width: 100%; border: 2px solid black;'>";
 
     tableText += "<tr>";
-    int index = 1;
+    int index = 0;
     for (int value : data) {
         tableText += QString("<td align='center' style='border: 2px solid black; min-width: 60px; padding: 10px;'>"
                              "%1 <sup style='font-size: 10px; font-weight: bold; color: black;'>%2</sup>"
@@ -83,7 +83,7 @@ void displayTableHTML(QTextEdit *textEdit, const std::vector<std::array<signed i
     textEdit->setReadOnly(false);
     QString tableText = "<table border='1' cellspacing='0' cellpadding='8' style='border-collapse: collapse; width: 100%; border: 2px solid black;'>";
 
-    int index = 1;
+    int index = 0;
     for (const auto &row : data) {
         tableText += "<tr>";
         for (signed int value : row) {
@@ -118,7 +118,7 @@ void browseAndUploadFile(QTextEdit *textEdit) {
 
     QTextStream in(&file);
     QString content;
-    int lineNumber = 1;
+    int lineNumber = 0;
 
     while (!in.atEnd()) {
         QString line = in.readLine();
diff --git a/gui/worker.cc b/gui/worker.cc
index ca3ec4b..2df4e17 100644
--- a/gui/worker.cc
+++ b/gui/worker.cc
@@ -2,66 +2,104 @@
 
 Worker::Worker(QObject *parent) : QObject(parent) {}
 
-void Worker::doWork() {
-    qDebug() << "Initializing...";
-    this->d = new Dram(0);
+void Worker::doWork()
+{
+	qDebug() << "Initializing...";
+	this->d = new Dram(0);
 	this->c = new Cache(this->d, 0);
-    this->if_stage = new IF(nullptr);
+	this->if_stage = new IF(nullptr);
 	this->id_stage = new ID(if_stage);
 	this->ex_stage = new EX(id_stage);
-    this->mm_stage = new MM(ex_stage);
-    this->wb_stage = new WB(mm_stage);
-    this->ct = new Controller(wb_stage, this->c, true);
-    
-    emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc());
-    emit dram_storage(this->d->view(0,32));
-    emit cache_storage(this->c->view(0,8));
-    emit register_storage(this->ct->get_gprs());
-    
-    signed int w;
-    w = 0x11223344;
-    this->d->write_word(MEM, w, 0x0);
-    this->c->write_word(MEM, w, 0x0);
-    this->ct->set_gprs(0, w);
+	this->mm_stage = new MM(ex_stage);
+	this->wb_stage = new WB(mm_stage);
+	this->ct = new Controller(wb_stage, this->c, true);
+
+	emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc());
+	emit dram_storage(this->d->view(0, 32));
+	emit cache_storage(this->c->view(0, 8));
+	emit register_storage(this->ct->get_gprs());
+
+	signed int b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14,
+		b15;
+	std::vector<signed int> p;
+
+	// I-TYPE              /    /    /   /
+	b0 = 0b00000010000000000001000000001101; // ADDI $2 $0 0x200;
+	b1 = 0b00000000000000010010100000001101; // ADDI $5 $0 0x1;
+	b2 = 0b00000000000000000010100010101101; // STORE $5 0($2);  (RAW HAZARD)!
+	// I-TYPE              /    /    /   /
+	b3 = 0b00000000000000100010100000001101; // ADDI $5 $0 0x2;   (RAW HAZARD)!
+	b4 = 0b00000000000000010010100010101101; // STORE $5 1($2);  (RAW HAZARD)!
+	// // I-TYPE           /    /    /   /
+	b5 = 0b00000000000000000010100000001101; // ADDI $5 $0 0x0;
+	// // I-TYPE           /    /    /   /
+	b6 = 0b00000000000000010011000000001101; // ADDI $6 $0 0x1;
+	// // J-TYPE                /    /   /
+	b7 = 0b00000000000000000011100000001010; // JRL CHECK
+	// // R-TYPE     /    /    /    /    /
+	b8 = 0b00000000000100100101000100000100; // ADD $9 $2 $5;
+	// // I-TYPE           /    /    /   /
+	b9 = 0b00000000000000000011101001000101; // LOAD $7 0($9); (RAW HAZARD)!
+	//  // I-TYPE           /    /    /   /
+	b10 = 0b00000000000000010100001001000101; // LOAD $8 1($9);
+	//  // R-TYPE     /    /    /    /    /
+	b11 = 0b00000000000011101000001110000100; // ADD $7 $7 $8;
+	// I-TYPE               /    /    /   /
+	b12 = 0b00000000000000000011101001101101; // STORE $7 0($9);
+	b13 = 0b00000010000000010010100101001101; // ADDI $5 $5 0x1;
+	//  // R-TYPE     /    /    /    /    /
+	b14 = 0b00000000000111100101001101000000; // CMP $6 $5
+	//  // J-TYPE                /    /   /
+	b15 = 0b11111111111111111100100000010110; // bgt LOOP
+
+	p = {b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15};
+	this->d->load(p);
 }
 
-Worker::~Worker() {
-    emit finished();
-    qDebug() << "Worker destructor called in thread:" << QThread::currentThread();
-    delete this->ct;
+Worker::~Worker()
+{
+	emit finished();
+	qDebug() << "Worker destructor called in thread:"
+			 << QThread::currentThread();
+	delete this->ct;
 	delete this->c;
 }
 
-
-void Worker::refreshDram() {
-    qDebug() << "Refreshing Dram";
-    emit dram_storage(this->d->view(0,32));
+void Worker::refreshDram()
+{
+	qDebug() << "Refreshing Dram";
+	emit dram_storage(this->d->view(0, 32));
 }
 
-void Worker::refreshCache() {
-    qDebug() << "Refreshing Dram";
-    emit cache_storage(this->c->view(0,8));
+void Worker::refreshCache()
+{
+	qDebug() << "Refreshing Dram";
+	emit cache_storage(this->c->view(0, 8));
 }
 
-void Worker::refreshRegisters() {
-    qDebug() << "Refreshing Registers";
-    emit register_storage(this->ct->get_gprs());
+void Worker::refreshRegisters()
+{
+	qDebug() << "Refreshing Registers";
+	emit register_storage(this->ct->get_gprs());
 }
 
-void Worker::runSteps(int steps) {
-    qDebug() << "Running for steps: " << steps;
-    this->ct->run_for(steps);
-    emit dram_storage(this->d->view(0,32));
-    emit cache_storage(this->c->view(0,8));
-    emit register_storage(this->ct->get_gprs());
-    emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc());
+void Worker::runSteps(int steps)
+{
+	qDebug() << "Running for steps: " << steps;
+	this->ct->run_for(steps);
+	emit dram_storage(this->d->view(0, 256));
+	emit cache_storage(this->c->view(0, 8));
+	emit register_storage(this->ct->get_gprs());
+	emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc());
 }
 
-void Worker::runStep() {
-    qDebug() << "Running for 1 step " ;
-    this->ct->advance(OK);
-    emit dram_storage(this->d->view(0,32));
-    emit cache_storage(this->c->view(0,8));
-    emit register_storage(this->ct->get_gprs());
-    emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc());
-}
\ No newline at end of file
+void Worker::runStep()
+{
+	qDebug() << "Running for 1 step ";
+	this->ct->advance(WAIT);
+	emit dram_storage(this->d->view(0, 256));
+	emit cache_storage(this->c->view(0, 8));
+	emit register_storage(this->ct->get_gprs());
+	qDebug() << "PC " << this->ct->get_pc();
+	emit clock_cycles(this->ct->get_clock_cycle(), this->ct->get_pc());
+}
diff --git a/src/sim/controller.cc b/src/sim/controller.cc
index cf8d02d..65e5676 100644
--- a/src/sim/controller.cc
+++ b/src/sim/controller.cc
@@ -19,7 +19,7 @@ void Controller::run_for(int number)
 {
 	int i;
 	for (i = 0; i < number; ++i) {
-		this->advance(OK);
+		this->advance(WAIT);
 	}
 }
 
@@ -38,7 +38,7 @@ InstrDTO *Controller::advance(Response p)
 	InstrDTO *r;
 	r = this->next->advance(p);
 	++this->clock_cycle;
-	
+
 	return r;
 }
 
diff --git a/src/sim/id.cc b/src/sim/id.cc
index 0df26f4..0c0be91 100644
--- a/src/sim/id.cc
+++ b/src/sim/id.cc
@@ -102,9 +102,10 @@ void ID::decode_R_type(signed int &s1, signed int &s2, signed int &s3)
 
 	r1 = this->read_guard(s1);
 	r2 = this->read_guard(s2);
-	this->write_guard(s3);
-
 	this->status = (r1 == OK && r2 == OK) ? OK : STALLED;
+
+	if (this->status == OK)
+		this->write_guard(s3);
 }
 
 void ID::decode_I_type(
@@ -123,7 +124,8 @@ void ID::decode_I_type(
 	r1 = this->read_guard(s1);
 	if (m != STORE && m != STOREV) {
 		this->status = r1;
-		this->write_guard(s2);
+		if (r1 == OK)
+			this->write_guard(s2);
 	} else
 		this->status = (this->read_guard(s2) == OK && r1 == OK) ? OK : STALLED;
 }
diff --git a/src/sim/stage.cc b/src/sim/stage.cc
index 24bdf75..2857e1f 100644
--- a/src/sim/stage.cc
+++ b/src/sim/stage.cc
@@ -28,6 +28,12 @@ InstrDTO *Stage::advance(Response p)
 	InstrDTO *s = nullptr;
 	Response n;
 
+	// std::cout << "advance: " << this->id << ": " << this->curr_instr << "?: " << p << ": " << this->checked_out.size() << ": ";
+	// if (curr_instr)
+	// 	std::cout << curr_instr->get_mnemonic();
+	// for (long unsigned int i = 0; i < this->checked_out.size(); ++i)
+	// 	std::cout << this->checked_out[i] << " ";
+	// std::cout << std::endl;	
 	if (this->curr_instr && this->status != OK) {
 		this->advance_helper();
 	}
diff --git a/tests/controller.cc b/tests/controller.cc
index c7e3c93..a009a70 100644
--- a/tests/controller.cc
+++ b/tests/controller.cc
@@ -350,6 +350,7 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 	CHECK(this->ct->get_pc() == 0xB);
 	CHECK(i->get_mnemonic() == ADD);
 	CHECK(i->get_instr_bits() == b8);
+	CHECK(this->ct->checked_out.front() == 0x7);
 
 	delete i;
 	i = this->ct->advance(WAIT); // RAW
@@ -373,6 +374,76 @@ TEST_CASE_METHOD(ControllerPipeFixture, "two num adder", "[full pipe]")
 	CHECK(this->ct->get_gprs().at(9) == 0x200);
 	CHECK(i->get_mnemonic() == LOAD);
 	CHECK(i->get_instr_bits() == b9);
+	CHECK(this->ct->checked_out.front() == 0x8);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 33);
+	CHECK(i->get_time_of(DCDE) == 34);
+	CHECK(i->get_time_of(EXEC) == 35);
+	CHECK(i->get_time_of(MEM) == 36);
+	CHECK(i->get_time_of(WRITE) == 37);
+	CHECK(i->get_s1() == 0x2);
+	CHECK(i->get_s2() == 0x0);
+	CHECK(i->get_s3() == 0x1);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(this->ct->get_gprs().at(7) == 0x1);
+	CHECK(this->ct->get_gprs().at(8) == 0x2);
+	CHECK(this->ct->get_gprs().at(9) == 0x200);
+	CHECK(i->get_mnemonic() == LOAD);
+	CHECK(i->get_instr_bits() == b10);
+	CHECK(this->ct->checked_out.front() == 0x7);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 34);
+	CHECK(i->get_time_of(DCDE) == 37);
+	CHECK(i->get_time_of(EXEC) == 38);
+	CHECK(i->get_time_of(MEM) == 39);
+	CHECK(i->get_time_of(WRITE) == 40);
+	CHECK(i->get_s1() == 0x3);
+	CHECK(i->get_s2() == 0x2);
+	CHECK(i->get_s3() == 0x1);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(this->ct->get_gprs().at(7) == 0x3);
+	CHECK(this->ct->get_gprs().at(8) == 0x2);
+	CHECK(this->ct->get_gprs().at(9) == 0x200);
+	CHECK(i->get_mnemonic() == ADD);
+	CHECK(i->get_instr_bits() == b11);
+
+	delete i;
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i == nullptr);
+	i = this->ct->advance(WAIT);
+	REQUIRE(i != nullptr);
+
+	CHECK(i->get_time_of(FETCH) == 37);
+	CHECK(i->get_time_of(DCDE) == 40);
+	CHECK(i->get_time_of(EXEC) == 41);
+	CHECK(i->get_time_of(MEM) == 42);
+	CHECK(i->get_time_of(WRITE) == 43);
+	CHECK(i->get_s1() == 0x200);
+	CHECK(i->get_s2() == 0x3);
+	CHECK(i->get_s3() == 0x0);
+	CHECK(this->ct->get_gprs().at(2) == 0x200);
+	CHECK(this->ct->get_gprs().at(6) == 0x1);
+	CHECK(this->ct->get_gprs().at(7) == 0x3);
+	CHECK(this->ct->get_gprs().at(8) == 0x2);
+	CHECK(this->ct->get_gprs().at(9) == 0x200);
+	CHECK(i->get_mnemonic() == STORE);
+	CHECK(i->get_instr_bits() == b12);
 
 	delete i;
 }
-- 
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