From f30196a1b0163fd359379307d94522d932031d96 Mon Sep 17 00:00:00 2001 From: bd Date: Thu, 20 Mar 2025 18:04:01 -0400 Subject: Make memory simulator an optional command, experiment with fixtures --- tests/dram.cc | 150 +++++++++++++++++++++++++++++++--------------------------- 1 file changed, 80 insertions(+), 70 deletions(-) (limited to 'tests/dram.cc') diff --git a/tests/dram.cc b/tests/dram.cc index 72a6d14..1fac82b 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -3,13 +3,21 @@ #include #include -TEST_CASE("Construct singleton dram", "[dram]") +class DramFixture { - Dram *d = new Dram(1, 1); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + public: + DramFixture() { this->d = new Dram(1, this->delay); } + ~DramFixture() { delete this->d; } + int delay = 3; + Dram *d; + std::array expected; + std::array actual; +}; + +TEST_CASE_METHOD(DramFixture, "Construct singleton dram", "[dram]") +{ + this->actual = this->d->view(0, 1)[0]; REQUIRE(expected == actual); - delete d; } TEST_CASE( @@ -51,12 +59,10 @@ TEST_CASE( actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } r = d->write_word(MEM, w, 0x00000000); CHECK(r == OK); - d->resolve(); expected.at(0) = w; actual = d->view(0, 1)[0]; @@ -86,19 +92,12 @@ TEST_CASE( actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } r = d->write_word(MEM, w, 0x00000000); REQUIRE(r == OK); - // clock cycle did NOT resolve yet! - // this fetch should not make progress r = d->write_word(FETCH, w, 0x00000001); - CHECK(r == WAIT); - - actual = d->view(0, 1)[0]; - CHECK(r == WAIT); - d->resolve(); + CHECK(r == OK); expected.at(0) = w; actual = d->view(0, 1)[0]; @@ -186,8 +185,7 @@ TEST_CASE( delete d; } -TEST_CASE( - "Construct singleton dram, store line in zero cycles", "[dram]") +TEST_CASE("Construct singleton dram, store line in zero cycles", "[dram]") { Dram *d = new Dram(1, 0); std::array expected = {0, 0, 0, 0}; @@ -195,7 +193,7 @@ TEST_CASE( CHECK(expected == actual); signed int w = 0x11223344; - expected = {w, w+1, w+2, w+3}; + expected = {w, w + 1, w + 2, w + 3}; Response r = d->write_line(MEM, expected, 0x00000000); CHECK(r == OK); @@ -206,8 +204,7 @@ TEST_CASE( delete d; } -TEST_CASE( - "Construct singleton dram, store line in three cycles", "[dram]") +TEST_CASE("Construct singleton dram, store line in three cycles", "[dram]") { int delay = 3; Dram *d = new Dram(1, delay); @@ -216,7 +213,7 @@ TEST_CASE( CHECK(expected == actual); signed int w = 0x11223344; - std::array written_line = {w, w+1, w+2, w+3}; + std::array written_line = {w, w + 1, w + 2, w + 3}; int i; Response r; @@ -252,7 +249,7 @@ TEST_CASE( CHECK(expected == actual); signed int w = 0x11223344; - std::array written_line = {w, w+1, w+2, w+3}; + std::array written_line = {w, w + 1, w + 2, w + 3}; int i; Response r; @@ -280,7 +277,7 @@ TEST_CASE( actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - written_line = {w+4, w+5, w+6, w+7}; + written_line = {w + 4, w + 5, w + 6, w + 7}; for (i = 0; i < delay; ++i) { r = d->write_line(FETCH, written_line, 0x00000001); @@ -314,7 +311,7 @@ TEST_CASE( CHECK(expected == actual); signed int w = 0x11223344; - std::array written_line = {w, w+1, w+2, w+3}; + std::array written_line = {w, w + 1, w + 2, w + 3}; int i; Response r; @@ -340,7 +337,7 @@ TEST_CASE( expected = written_line; REQUIRE(expected == actual); - written_line = {w+4, w+5, w+6, w+7}; + written_line = {w + 4, w + 5, w + 6, w + 7}; for (i = 0; i < delay; ++i) { r = d->write_line(FETCH, written_line, 0x00000001); CHECK(r == WAIT); @@ -366,7 +363,10 @@ TEST_CASE( delete d; } -TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, read in 0 cycles", "[dram]") +TEST_CASE( + "Construct singleton dram, write a line to an address in 0 cycles, read in " + "0 cycles", + "[dram]") { Dram *d = new Dram(1, 0); std::array expected = {0, 0, 0, 0}; @@ -374,7 +374,7 @@ TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, rea CHECK(expected == actual); signed int w = 0x11223311; - expected = {w, w+1, w+2, w+3}; + expected = {w, w + 1, w + 2, w + 3}; int addr = 0x00000000; d->write_line(MEM, expected, addr); @@ -397,7 +397,10 @@ TEST_CASE("Construct singleton dram, write a line to an address in 0 cycles, rea delete d; } -TEST_CASE("Construct singleton dram, write a line to an address in three cycles, read it in three cycles", "[dram]") +TEST_CASE( + "Construct singleton dram, write a line to an address in three cycles, " + "read it in three cycles", + "[dram]") { int delay = 3; Dram *d = new Dram(1, delay); @@ -406,13 +409,13 @@ TEST_CASE("Construct singleton dram, write a line to an address in three cycles, CHECK(expected == actual); signed int w = 0x11223311; - expected = {w, w+1, w+2, w+3}; + expected = {w, w + 1, w + 2, w + 3}; int addr = 0x00000000; - + int i; Response r; - - for(i=0; iwrite_line(MEM, expected, addr); d->resolve(); } @@ -434,7 +437,9 @@ TEST_CASE("Construct singleton dram, write a line to an address in three cycles, } TEST_CASE( - "Construct singleton dram, store line in 3 cycles, read line in 3 cycles with no conflict","[dram]") + "Construct singleton dram, store line in 3 cycles, read line in 3 cycles " + "with no conflict", + "[dram]") { int delay = 3; Dram *d = new Dram(1, delay); @@ -443,12 +448,12 @@ TEST_CASE( CHECK(expected == actual); signed int w = 0x11223311; - expected = {w, w+1, w+2, w+3}; + expected = {w, w + 1, w + 2, w + 3}; int addr = 0x00000000; - + int i; Response r; - for(int j=0; jwrite_line(MEM, expected, addr); d->resolve(); } @@ -465,11 +470,11 @@ TEST_CASE( r = d->read_line(MEM, 0x00000000, actual); REQUIRE(r == OK); r = d->read_line(FETCH, 0x00000003, actual); - CHECK(r == WAIT); + CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); - actual = {0,0,0,0}; + actual = {0, 0, 0, 0}; for (i = 0; i < delay; ++i) { r = d->read_line(FETCH, 0x00000000, actual); CHECK(r == WAIT); @@ -483,13 +488,14 @@ TEST_CASE( CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); - - delete d; + delete d; } TEST_CASE( - "Construct singleton dram, store line in 3 cycles, read line in 3 cycles with much conflict","[dram]") + "Construct singleton dram, store line in 3 cycles, read line in 3 cycles " + "with much conflict", + "[dram]") { int delay = 3; Dram *d = new Dram(1, delay); @@ -498,19 +504,18 @@ TEST_CASE( CHECK(expected == actual); signed int w = 0x11223311; - expected = {w, w+1, w+2, w+3}; + expected = {w, w + 1, w + 2, w + 3}; int addr = 0x00000000; - + int i; Response r; - for(int j=0; jwrite_line(MEM, expected, addr); d->resolve(); } r = d->write_line(MEM, expected, addr++); d->resolve(); - for (i = 0; i < delay; ++i) { r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); @@ -524,11 +529,11 @@ TEST_CASE( r = d->read_line(MEM, 0x00000000, actual); REQUIRE(r == OK); r = d->read_line(FETCH, 0x00000003, actual); - CHECK(r == WAIT); + CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); - actual = {0,0,0,0}; + actual = {0, 0, 0, 0}; for (i = 0; i < delay; ++i) { r = d->read_line(FETCH, 0x00000000, actual); CHECK(r == WAIT); @@ -545,13 +550,14 @@ TEST_CASE( CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); - - delete d; + delete d; } - -TEST_CASE("Construct singleton dram, write a line to an address one element at a time, read it in zero cycles", "[dram]") +TEST_CASE( + "Construct singleton dram, write a line to an address one element at a " + "time, read it in zero cycles", + "[dram]") { Dram *d = new Dram(1, 0); std::array expected = {0, 0, 0, 0}; @@ -560,7 +566,7 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a signed int w = 0x11223311; int addr = 0x00000000; - for(int i=0; iwrite_word(MEM, w, addr++); CHECK(r == OK); expected.at(i) = w++; @@ -585,7 +591,10 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a delete d; } -TEST_CASE("Construct singleton dram, write a line to an address one element at a time in 12 cycles, read it in three cycles", "[dram]") +TEST_CASE( + "Construct singleton dram, write a line to an address one element at a " + "time in 12 cycles, read it in three cycles", + "[dram]") { int delay = 3; Dram *d = new Dram(1, delay); @@ -597,8 +606,8 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a int addr = 0x00000000; int i; Response r; - for(i=0; iwrite_word(MEM, w, addr); d->resolve(); } @@ -622,7 +631,9 @@ TEST_CASE("Construct singleton dram, write a line to an address one element at a } TEST_CASE( - "Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with no conflict","[dram]") + "Construct singleton dram, store line one element at a time in 12 cycles, " + "read line in 3 cycles with no conflict", + "[dram]") { int delay = 3; Dram *d = new Dram(1, delay); @@ -634,8 +645,8 @@ TEST_CASE( int addr = 0x00000000; int i; Response r; - for(i=0; iwrite_word(MEM, w, addr); d->resolve(); } @@ -654,11 +665,11 @@ TEST_CASE( r = d->read_line(MEM, 0x00000000, actual); REQUIRE(r == OK); r = d->read_line(FETCH, 0x00000003, actual); - CHECK(r == WAIT); + CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); - actual = {0,0,0,0}; + actual = {0, 0, 0, 0}; for (i = 0; i < delay; ++i) { r = d->read_line(FETCH, 0x00000000, actual); CHECK(r == WAIT); @@ -672,13 +683,14 @@ TEST_CASE( CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); - - delete d; + delete d; } TEST_CASE( - "Construct singleton dram, store line one element at a time in 12 cycles, read line in 3 cycles with much conflict","[dram]") + "Construct singleton dram, store line one element at a time in 12 cycles, " + "read line in 3 cycles with much conflict", + "[dram]") { int delay = 3; Dram *d = new Dram(1, delay); @@ -690,8 +702,8 @@ TEST_CASE( int addr = 0x00000000; int i; Response r; - for(i=0; iwrite_word(MEM, w, addr); d->resolve(); } @@ -713,11 +725,11 @@ TEST_CASE( r = d->read_line(MEM, 0x00000000, actual); REQUIRE(r == OK); r = d->read_line(FETCH, 0x00000003, actual); - CHECK(r == WAIT); + CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); - actual = {0,0,0,0}; + actual = {0, 0, 0, 0}; for (i = 0; i < delay; ++i) { r = d->read_line(FETCH, 0x00000000, actual); CHECK(r == WAIT); @@ -734,12 +746,10 @@ TEST_CASE( CHECK(r == WAIT); d->resolve(); REQUIRE(expected == actual); - - delete d; + delete d; } - TEST_CASE("Sidedoor bypasses delay", "[dram]") { int delay = 3; -- cgit v1.2.3 From cf3ac49639bef5082489068e2d92a4d86f42080b Mon Sep 17 00:00:00 2001 From: bd Date: Thu, 20 Mar 2025 19:28:57 -0400 Subject: Rewrite all Dram tests to use Fixture --- inc/dram.h | 2 +- src/cli/cli.cc | 2 +- src/storage/dram.cc | 4 +- tests/cache.cc | 12 +- tests/dram.cc | 763 ++++++++++++++-------------------------------------- 5 files changed, 214 insertions(+), 569 deletions(-) (limited to 'tests/dram.cc') diff --git a/inc/dram.h b/inc/dram.h index 2771c3e..c7f927a 100644 --- a/inc/dram.h +++ b/inc/dram.h @@ -14,7 +14,7 @@ class Dram : public Storage * @param The number of clock cycles each access takes. * @return A new memory object. */ - Dram(int lines, int delay); + Dram(int delay); ~Dram(); Response diff --git a/src/cli/cli.cc b/src/cli/cli.cc index 41ac57c..e25b316 100644 --- a/src/cli/cli.cc +++ b/src/cli/cli.cc @@ -211,7 +211,7 @@ void Cli::initialize() if (this->cache != nullptr) delete this->cache; - Dram *d = new Dram(MEM_LINES, MEM_DELAY); + Dram *d = new Dram(MEM_DELAY); this->cache = new Cache(d, L1_CACHE_DELAY); this->cycle = 1; } diff --git a/src/storage/dram.cc b/src/storage/dram.cc index 56eec47..20db47e 100644 --- a/src/storage/dram.cc +++ b/src/storage/dram.cc @@ -8,10 +8,10 @@ #include #include -Dram::Dram(int lines, int delay) +Dram::Dram(int delay) { this->data = new std::vector>; - this->data->resize(lines); + this->data->resize(MEM_LINES); this->delay = delay; this->is_waiting = false; this->lower = nullptr; diff --git a/tests/cache.cc b/tests/cache.cc index daaec90..1fc5209 100644 --- a/tests/cache.cc +++ b/tests/cache.cc @@ -15,7 +15,7 @@ TEST_CASE("Constructor singleton cache", "[cache]") TEST_CASE("no delay stores instantly", "[cache]") { int delay = 0; - Dram *d = new Dram(MEM_LINES, delay); + Dram *d = new Dram(delay); Cache *c = new Cache(d, delay); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; @@ -43,7 +43,7 @@ TEST_CASE("no delay stores instantly", "[cache]") TEST_CASE("cache takes \"forever\"", "[cache]") { int delay = 0; - Dram *d = new Dram(MEM_LINES, delay); + Dram *d = new Dram(delay); Cache *c = new Cache(d, delay + 2); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; @@ -79,7 +79,7 @@ TEST_CASE("cache takes \"forever\"", "[cache]") TEST_CASE("dram takes \"forever\"", "[cache]") { int delay = 0; - Dram *d = new Dram(MEM_LINES, delay + 2); + Dram *d = new Dram(delay + 2); Cache *c = new Cache(d, delay); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; @@ -115,7 +115,7 @@ TEST_CASE("dram takes \"forever\"", "[cache]") TEST_CASE("dram and cache take \"forever\"", "[cache]") { int delay = 2; - Dram *d = new Dram(MEM_LINES, delay + 2); + Dram *d = new Dram(delay + 2); Cache *c = new Cache(d, delay); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; @@ -162,7 +162,7 @@ TEST_CASE( "dram takes \"forever\", two concurrent requests same index", "[cache]") { int delay = 0; - Dram *d = new Dram(MEM_LINES, delay + 2); + Dram *d = new Dram(delay + 2); Cache *c = new Cache(d, delay); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; @@ -217,7 +217,7 @@ TEST_CASE( "[cache]") { int delay = 0; - Dram *d = new Dram(MEM_LINES, delay + 2); + Dram *d = new Dram(delay + 2); Cache *c = new Cache(d, delay); std::array expected = {0, 0, 0, 0}; std::array actual = d->view(0, 1)[0]; diff --git a/tests/dram.cc b/tests/dram.cc index 1fac82b..4dcdb31 100644 --- a/tests/dram.cc +++ b/tests/dram.cc @@ -6,783 +6,428 @@ class DramFixture { public: - DramFixture() { this->d = new Dram(1, this->delay); } + DramFixture() + { + this->delay = 3; + this->d = new Dram(this->delay); + this->expected = {0, 0, 0, 0}; + this->actual = this->d->view(0, 1)[0]; + } ~DramFixture() { delete this->d; } - int delay = 3; + int delay; Dram *d; std::array expected; std::array actual; }; -TEST_CASE_METHOD(DramFixture, "Construct singleton dram", "[dram]") -{ - this->actual = this->d->view(0, 1)[0]; - REQUIRE(expected == actual); -} - -TEST_CASE( - "Construct singleton dram, store 0th element in zero cycles", "[dram]") -{ - Dram *d = new Dram(1, 0); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223344; - - Response r = d->write_word(MEM, w, 0x00000000); - CHECK(r == OK); - - expected.at(0) = w; - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - - delete d; -} - -TEST_CASE( - "Construct singleton dram, store 0th element in three cycles", "[dram]") +TEST_CASE_METHOD(DramFixture, "store 0th element in DELAY cycles", "[dram]") { - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Response r; + signed int w; + int i; CHECK(expected == actual); - signed int w = 0x11223344; + w = 0x11223344; + for (i = 0; i < this->delay; ++i) { + r = this->d->write_word(MEM, w, 0x0); + this->d->resolve(); - int i; - Response r; - for (i = 0; i < delay; ++i) { - r = d->write_word(MEM, w, 0x00000000); + // check response CHECK(r == WAIT); - + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); } - r = d->write_word(MEM, w, 0x00000000); - CHECK(r == OK); + r = this->d->write_word(MEM, w, 0x0); + this->d->resolve(); + CHECK(r == OK); expected.at(0) = w; - actual = d->view(0, 1)[0]; + actual = this->d->view(0, 1)[0]; REQUIRE(expected == actual); - - delete d; } -TEST_CASE( - "Construct singleton dram, store 0, 1th element in three cycles no " - "conflict", +TEST_CASE_METHOD( + DramFixture, + "store 0th, 1st element in DELAY cycles, no conflict", "[dram]") { - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Response r; + signed int w; + int i; CHECK(expected == actual); - signed int w = 0x11223344; + w = 0x11223344; + for (i = 0; i < this->delay; ++i) { + r = this->d->write_word(MEM, w, 0x0); + this->d->resolve(); - int i; - Response r; - for (i = 0; i < delay; ++i) { - r = d->write_word(MEM, w, 0x00000000); + // check response CHECK(r == WAIT); - + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); } - r = d->write_word(MEM, w, 0x00000000); + r = d->write_word(MEM, w, 0x0); REQUIRE(r == OK); - r = d->write_word(FETCH, w, 0x00000001); - CHECK(r == OK); + // clock cycle did NOT resolve yet! + // this fetch should not make progress + r = d->write_word(FETCH, w, 0x1); + CHECK(r == WAIT); + this->d->resolve(); expected.at(0) = w; actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - for (i = 0; i < delay; ++i) { - r = d->write_word(FETCH, w, 0x00000001); - CHECK(r == WAIT); + for (i = 0; i < this->delay; ++i) { + r = this->d->write_word(FETCH, w, 0x1); + this->d->resolve(); + // check response + CHECK(r == WAIT); + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } - r = d->write_word(FETCH, w, 0x00000001); - actual = d->view(0, 1)[0]; + r = d->write_word(FETCH, w, 0x1); CHECK(r == OK); + this->d->resolve(); - expected.at(1) = w; actual = d->view(0, 1)[0]; + expected.at(1) = w; REQUIRE(expected == actual); - - delete d; } -TEST_CASE( - "Construct singleton dram, store 0, 1th element in three cycles much " - "conflict", - "[dram]") +TEST_CASE_METHOD( + DramFixture, "store 0th element in DELAY cycles with conflict", "[dram]") { - int delay = 2; - Dram *d = new Dram(1, 2); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Response r; + signed int w; + int i; CHECK(expected == actual); - signed int w = 0x11223344; - - int i; - Response r; - for (i = 0; i < delay; ++i) { - r = d->write_word(MEM, w, 0x00000000); + w = 0x11223344; + for (i = 0; i < this->delay; ++i) { + r = this->d->write_word(MEM, w, 0x0); CHECK(r == WAIT); - - r = d->write_word(FETCH, w, 0x00000001); + r = this->d->write_word(FETCH, w, 0x1); CHECK(r == WAIT); + this->d->resolve(); + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } - r = d->write_word(MEM, w, 0x00000000); - CHECK(r == OK); - r = d->write_word(FETCH, w, 0x00000001); + r = d->write_word(MEM, w, 0x0); + REQUIRE(r == OK); + // clock cycle did NOT resolve yet! + // this fetch should not make progress + r = d->write_word(FETCH, w, 0x1); CHECK(r == WAIT); - d->resolve(); + this->d->resolve(); - actual = d->view(0, 1)[0]; expected.at(0) = w; + actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - for (i = 0; i < delay; ++i) { - r = d->write_word(FETCH, w, 0x00000001); - CHECK(r == WAIT); + for (i = 0; i < this->delay; ++i) { + r = this->d->write_word(FETCH, w, 0x1); + this->d->resolve(); - r = d->write_word(MEM, w, 0x00000003); + // check response CHECK(r == WAIT); - + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } - r = d->write_word(FETCH, w, 0x00000001); - actual = d->view(0, 1)[0]; - CHECK(r == OK); - r = d->write_word(MEM, w, 0x00000003); - CHECK(r == WAIT); - - expected.at(1) = w; - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - - delete d; -} - -TEST_CASE("Construct singleton dram, store line in zero cycles", "[dram]") -{ - Dram *d = new Dram(1, 0); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223344; - expected = {w, w + 1, w + 2, w + 3}; - - Response r = d->write_line(MEM, expected, 0x00000000); + r = d->write_word(FETCH, w, 0x1); CHECK(r == OK); + this->d->resolve(); actual = d->view(0, 1)[0]; + expected.at(1) = w; REQUIRE(expected == actual); - - delete d; } -TEST_CASE("Construct singleton dram, store line in three cycles", "[dram]") +TEST_CASE_METHOD(DramFixture, "store line in DELAY cycles", "[dram]") { - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Response r; + signed int w; + int i; + std::array buffer; CHECK(expected == actual); - signed int w = 0x11223344; - std::array written_line = {w, w + 1, w + 2, w + 3}; + w = 0x11223344; + buffer = {w, w + 1, w + 2, w + 3}; + for (i = 0; i < this->delay; ++i) { + r = this->d->write_line(MEM, buffer, 0x0); + this->d->resolve(); - int i; - Response r; - for (i = 0; i < delay; ++i) { - r = d->write_line(MEM, written_line, 0x00000000); + // check response CHECK(r == WAIT); - + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } - r = d->write_line(MEM, written_line, 0x00000000); + r = d->write_line(MEM, buffer, 0x0); CHECK(r == OK); - d->resolve(); - expected = written_line; actual = d->view(0, 1)[0]; + expected = buffer; REQUIRE(expected == actual); - - delete d; } -TEST_CASE( - "Construct singleton dram, store line in three cycles no " - "conflict", - "[dram]") +TEST_CASE_METHOD( + DramFixture, "store line in DELAY cycles no conflict", "[dram]") { - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Response r; + signed int w; + int i; + std::array buffer; CHECK(expected == actual); - signed int w = 0x11223344; - std::array written_line = {w, w + 1, w + 2, w + 3}; + w = 0x11223344; + buffer = {w, w + 1, w + 2, w + 3}; + for (i = 0; i < this->delay; ++i) { + r = this->d->write_line(MEM, buffer, 0x0); + this->d->resolve(); - int i; - Response r; - for (i = 0; i < delay; ++i) { - r = d->write_line(MEM, written_line, 0x00000000); + // check response CHECK(r == WAIT); - + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } - r = d->write_line(MEM, written_line, 0x00000000); + r = this->d->write_line(MEM, buffer, 0x0); REQUIRE(r == OK); // clock cycle did NOT resolve yet! // this fetch should not make progress - r = d->write_line(FETCH, written_line, 0x00000001); - CHECK(r == WAIT); - - actual = d->view(0, 1)[0]; + r = this->d->write_line(FETCH, buffer, 0x1); CHECK(r == WAIT); d->resolve(); - expected = written_line; + expected = buffer; actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - written_line = {w + 4, w + 5, w + 6, w + 7}; + buffer = {w + 4, w + 5, w + 6, w + 7}; + for (i = 0; i < this->delay; ++i) { + r = this->d->write_line(FETCH, buffer, 0x1); + this->d->resolve(); - for (i = 0; i < delay; ++i) { - r = d->write_line(FETCH, written_line, 0x00000001); + // check response CHECK(r == WAIT); - + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } - r = d->write_line(FETCH, written_line, 0x00000001); - actual = d->view(0, 1)[0]; + r = this->d->write_line(FETCH, buffer, 0x1); CHECK(r == OK); + d->resolve(); - expected = written_line; + expected = buffer; actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - - delete d; } -TEST_CASE( - "Construct singleton dram, store line in three cycles much " - "conflict", - "[dram]") +TEST_CASE_METHOD( + DramFixture, "store line in DELAY cycles with conflict", "[dram]") { - int delay = 2; - Dram *d = new Dram(1, 2); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Response r; + signed int w; + int i; + std::array buffer; CHECK(expected == actual); - signed int w = 0x11223344; - std::array written_line = {w, w + 1, w + 2, w + 3}; - - int i; - Response r; - for (i = 0; i < delay; ++i) { - r = d->write_line(MEM, written_line, 0x00000000); + w = 0x11223344; + buffer = {w, w + 1, w + 2, w + 3}; + for (i = 0; i < this->delay; ++i) { + r = this->d->write_line(MEM, buffer, 0x0); CHECK(r == WAIT); - - r = d->write_line(FETCH, written_line, 0x00000001); + r = d->write_line(FETCH, buffer, 0x1); CHECK(r == WAIT); + this->d->resolve(); + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } - r = d->write_line(MEM, written_line, 0x00000000); + r = d->write_line(MEM, buffer, 0x0); CHECK(r == OK); - r = d->write_line(FETCH, written_line, 0x00000001); + // clock cycle did NOT resolve yet! + // this fetch should not make progress + r = d->write_line(FETCH, buffer, 0x01); CHECK(r == WAIT); d->resolve(); actual = d->view(0, 1)[0]; - expected = written_line; + expected = buffer; REQUIRE(expected == actual); - written_line = {w + 4, w + 5, w + 6, w + 7}; - for (i = 0; i < delay; ++i) { - r = d->write_line(FETCH, written_line, 0x00000001); - CHECK(r == WAIT); + buffer = {w + 4, w + 5, w + 6, w + 7}; + for (i = 0; i < this->delay; ++i) { + r = this->d->write_line(FETCH, buffer, 0x1); + this->d->resolve(); - r = d->write_line(MEM, written_line, 0x00000003); + // check response CHECK(r == WAIT); - + // check for early modifications actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - d->resolve(); } - r = d->write_line(FETCH, written_line, 0x00000001); - actual = d->view(0, 1)[0]; + r = this->d->write_line(FETCH, buffer, 0x1); CHECK(r == OK); - r = d->write_line(MEM, written_line, 0x00000003); - CHECK(r == WAIT); + d->resolve(); - expected = written_line; + expected = buffer; actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - - delete d; -} - -TEST_CASE( - "Construct singleton dram, write a line to an address in 0 cycles, read in " - "0 cycles", - "[dram]") -{ - Dram *d = new Dram(1, 0); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223311; - expected = {w, w + 1, w + 2, w + 3}; - int addr = 0x00000000; - d->write_line(MEM, expected, addr); - - Response r = d->read_line(MEM, 0x00000000, actual); - CHECK(r == OK); - REQUIRE(expected == actual); - - r = d->read_line(MEM, 0x00000001, actual); - CHECK(r == OK); - REQUIRE(expected == actual); - - r = d->read_line(MEM, 0x00000002, actual); - CHECK(r == OK); - REQUIRE(expected == actual); - - r = d->read_line(MEM, 0x00000003, actual); - CHECK(r == OK); - REQUIRE(expected == actual); - - delete d; } -TEST_CASE( - "Construct singleton dram, write a line to an address in three cycles, " - "read it in three cycles", - "[dram]") +TEST_CASE_METHOD( + DramFixture, "store line in DELAY cycles, read in DELAY cycles", "[dram]") { - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Response r; + signed int w; + int i, addr; CHECK(expected == actual); - signed int w = 0x11223311; + w = 0x11223311; + addr = 0x0; expected = {w, w + 1, w + 2, w + 3}; - int addr = 0x00000000; - - int i; - Response r; - - for (i = 0; i < delay; ++i) { + for (i = 0; i < this->delay; ++i) { r = d->write_line(MEM, expected, addr); - d->resolve(); - } - r = d->write_line(MEM, expected, addr); - d->resolve(); - - for (i = 0; i < delay; ++i) { - r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); - REQUIRE(expected != actual); d->resolve(); } - - r = d->read_line(MEM, 0x00000000, actual); + r = d->write_line(MEM, expected, addr); CHECK(r == OK); d->resolve(); - REQUIRE(expected == actual); - delete d; -} - -TEST_CASE( - "Construct singleton dram, store line in 3 cycles, read line in 3 cycles " - "with no conflict", - "[dram]") -{ - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - signed int w = 0x11223311; - expected = {w, w + 1, w + 2, w + 3}; - int addr = 0x00000000; - - int i; - Response r; - for (int j = 0; j < delay; ++j) { - r = d->write_line(MEM, expected, addr); + for (i = 0; i < this->delay; ++i) { + r = d->read_line(MEM, addr, actual); d->resolve(); - } - r = d->write_line(MEM, expected, addr++); - d->resolve(); - for (i = 0; i < delay; ++i) { - r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); - d->resolve(); } - r = d->read_line(MEM, 0x00000000, actual); - REQUIRE(r == OK); - r = d->read_line(FETCH, 0x00000003, actual); - CHECK(r == WAIT); + r = d->read_line(MEM, addr, actual); d->resolve(); - REQUIRE(expected == actual); - - actual = {0, 0, 0, 0}; - for (i = 0; i < delay; ++i) { - r = d->read_line(FETCH, 0x00000000, actual); - CHECK(r == WAIT); - REQUIRE(expected != actual); - d->resolve(); - } - r = d->read_line(FETCH, 0x00000000, actual); - REQUIRE(r == OK); - r = d->read_line(MEM, 0x00000002, actual); - CHECK(r == WAIT); - d->resolve(); + CHECK(r == OK); REQUIRE(expected == actual); - - delete d; } -TEST_CASE( - "Construct singleton dram, store line in 3 cycles, read line in 3 cycles " - "with much conflict", +TEST_CASE_METHOD( + DramFixture, + "store line in DELAY cycles, read in DELAY cycles with conflict", "[dram]") { - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; + Response r; + signed int w; + int i, addr; CHECK(expected == actual); - signed int w = 0x11223311; + w = 0x11223311; + addr = 0x0; expected = {w, w + 1, w + 2, w + 3}; - int addr = 0x00000000; - - int i; - Response r; - for (int j = 0; j < delay; ++j) { - r = d->write_line(MEM, expected, addr); - d->resolve(); - } - r = d->write_line(MEM, expected, addr++); - d->resolve(); - for (i = 0; i < delay; ++i) { - r = d->read_line(MEM, 0x00000000, actual); - CHECK(r == WAIT); - REQUIRE(expected != actual); - r = d->read_line(FETCH, 0x00000002, actual); + r = d->write_line(MEM, expected, addr); CHECK(r == WAIT); - REQUIRE(expected != actual); - d->resolve(); - } - - r = d->read_line(MEM, 0x00000000, actual); - REQUIRE(r == OK); - r = d->read_line(FETCH, 0x00000003, actual); - CHECK(r == WAIT); - d->resolve(); - REQUIRE(expected == actual); - actual = {0, 0, 0, 0}; - for (i = 0; i < delay; ++i) { - r = d->read_line(FETCH, 0x00000000, actual); - CHECK(r == WAIT); - REQUIRE(expected != actual); - r = d->read_line(MEM, 0x00000002, actual); + r = d->read_line(FETCH, addr, actual); CHECK(r == WAIT); - REQUIRE(expected != actual); + d->resolve(); } - - r = d->read_line(FETCH, 0x00000000, actual); - REQUIRE(r == OK); - r = d->read_line(MEM, 0x00000002, actual); + r = d->write_line(MEM, expected, addr); + CHECK(r == OK); + r = d->read_line(FETCH, addr, actual); CHECK(r == WAIT); d->resolve(); - REQUIRE(expected == actual); - - delete d; -} - -TEST_CASE( - "Construct singleton dram, write a line to an address one element at a " - "time, read it in zero cycles", - "[dram]") -{ - Dram *d = new Dram(1, 0); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223311; - int addr = 0x00000000; - for (int i = 0; i < LINE_SIZE; ++i) { - Response r = d->write_word(MEM, w, addr++); - CHECK(r == OK); - expected.at(i) = w++; - } - - Response r = d->read_line(MEM, 0x00000000, actual); - CHECK(r == OK); - REQUIRE(expected == actual); - - r = d->read_line(MEM, 0x00000001, actual); - CHECK(r == OK); - REQUIRE(expected == actual); - r = d->read_line(MEM, 0x00000002, actual); - CHECK(r == OK); - REQUIRE(expected == actual); - - r = d->read_line(MEM, 0x00000003, actual); - CHECK(r == OK); - REQUIRE(expected == actual); - - delete d; -} - -TEST_CASE( - "Construct singleton dram, write a line to an address one element at a " - "time in 12 cycles, read it in three cycles", - "[dram]") -{ - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223311; - int addr = 0x00000000; - int i; - Response r; - for (i = 0; i < LINE_SIZE; ++i) { - for (int j = 0; j < delay; ++j) { - r = d->write_word(MEM, w, addr); - d->resolve(); - } - r = d->write_word(MEM, w, addr++); + for (i = 0; i < this->delay; ++i) { + r = d->read_line(MEM, addr, actual); d->resolve(); - expected.at(i) = w++; - } - for (i = 0; i < delay; ++i) { - r = d->read_line(MEM, 0x00000000, actual); CHECK(r == WAIT); REQUIRE(expected != actual); - d->resolve(); } - r = d->read_line(MEM, 0x00000000, actual); - CHECK(r == OK); + r = d->read_line(MEM, addr, actual); d->resolve(); + + CHECK(r == OK); REQUIRE(expected == actual); - delete d; } -TEST_CASE( - "Construct singleton dram, store line one element at a time in 12 cycles, " - "read line in 3 cycles with no conflict", +TEST_CASE_METHOD( + DramFixture, + "store line in DELAY cycles, read one element at a time in DELAY cycles " + "with conflict", "[dram]") { - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223311; - int addr = 0x00000000; - int i; Response r; - for (i = 0; i < LINE_SIZE; ++i) { - for (int j = 0; j < delay; ++j) { - r = d->write_word(MEM, w, addr); - d->resolve(); - } - r = d->write_word(MEM, w, addr++); - d->resolve(); - expected.at(i) = w++; - } + signed int w, a; + int i, j, addr; + CHECK(expected == actual); - for (i = 0; i < delay; ++i) { - r = d->read_line(MEM, 0x00000000, actual); + w = 0x11223311; + a = 0x0; + addr = 0x0; + expected = {w, w + 1, w + 2, w + 3}; + for (i = 0; i < this->delay; ++i) { + r = d->write_line(MEM, expected, addr); CHECK(r == WAIT); - REQUIRE(expected != actual); d->resolve(); } - - r = d->read_line(MEM, 0x00000000, actual); - REQUIRE(r == OK); - r = d->read_line(FETCH, 0x00000003, actual); - CHECK(r == WAIT); + r = d->write_line(MEM, expected, addr); + CHECK(r == OK); d->resolve(); - REQUIRE(expected == actual); - actual = {0, 0, 0, 0}; - for (i = 0; i < delay; ++i) { - r = d->read_line(FETCH, 0x00000000, actual); - CHECK(r == WAIT); - REQUIRE(expected != actual); - d->resolve(); - } - - r = d->read_line(FETCH, 0x00000000, actual); - REQUIRE(r == OK); - r = d->read_line(MEM, 0x00000002, actual); - CHECK(r == WAIT); - d->resolve(); + actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - delete d; -} - -TEST_CASE( - "Construct singleton dram, store line one element at a time in 12 cycles, " - "read line in 3 cycles with much conflict", - "[dram]") -{ - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223311; - int addr = 0x00000000; - int i; - Response r; for (i = 0; i < LINE_SIZE; ++i) { - for (int j = 0; j < delay; ++j) { - r = d->write_word(MEM, w, addr); + for (j = 0; j < this->delay; ++j) { + r = d->read_word(MEM, addr, a); d->resolve(); - } - r = d->write_word(MEM, w, addr++); - d->resolve(); - expected.at(i) = w++; - } - for (i = 0; i < delay; ++i) { - r = d->read_line(MEM, 0x00000000, actual); - CHECK(r == WAIT); - REQUIRE(expected != actual); - r = d->read_line(FETCH, 0x00000002, actual); - CHECK(r == WAIT); - REQUIRE(expected != actual); + CHECK(r == WAIT); + REQUIRE(0x0 == a); + } + r = d->read_word(MEM, addr++, a); d->resolve(); - } - - r = d->read_line(MEM, 0x00000000, actual); - REQUIRE(r == OK); - r = d->read_line(FETCH, 0x00000003, actual); - CHECK(r == WAIT); - d->resolve(); - REQUIRE(expected == actual); + CHECK(r == OK); + REQUIRE(w++ == a); - actual = {0, 0, 0, 0}; - for (i = 0; i < delay; ++i) { - r = d->read_line(FETCH, 0x00000000, actual); - CHECK(r == WAIT); - REQUIRE(expected != actual); - r = d->read_line(MEM, 0x00000002, actual); - CHECK(r == WAIT); - REQUIRE(expected != actual); - d->resolve(); + a = 0; } - - r = d->read_line(FETCH, 0x00000000, actual); - REQUIRE(r == OK); - r = d->read_line(MEM, 0x00000002, actual); - CHECK(r == WAIT); - d->resolve(); - REQUIRE(expected == actual); - - delete d; } -TEST_CASE("Sidedoor bypasses delay", "[dram]") +TEST_CASE_METHOD(DramFixture, "Sidedoor bypasses delay", "[dram]") { - int delay = 3; - Dram *d = new Dram(1, delay); - std::array expected = {0, 0, 0, 0}; - std::array actual = d->view(0, 1)[0]; - CHECK(expected == actual); - - signed int w = 0x11223344; - - int i; Response r; - for (i = 0; i < delay - 1; ++i) { - r = d->write_word(MEM, w, 0x00000000); - CHECK(r == WAIT); - - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); - d->resolve(); - } - - r = d->write_word(MEM, w, 0x00000000); - CHECK(r == WAIT); - actual = d->view(0, 1)[0]; - REQUIRE(expected == actual); + signed int w; + CHECK(expected == actual); - r = d->write_word(SIDE, w, 0x00000001); - actual = d->view(0, 1)[0]; + w = 0x11223344; + r = this->d->write_word(SIDE, w, 0x0); CHECK(r == OK); - expected.at(1) = w; + expected.at(0) = w; actual = d->view(0, 1)[0]; REQUIRE(expected == actual); - - delete d; } -- cgit v1.2.3