From b81c86b438123457be86af2e7c24375856afa742 Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 26 Mar 2025 12:21:52 -0400 Subject: Add fetch stage implementation, tests, program loading, DTO object --- tests/controller.cc | 14 +++++++- tests/if.cc | 99 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+), 1 deletion(-) create mode 100644 tests/if.cc (limited to 'tests') diff --git a/tests/controller.cc b/tests/controller.cc index a1b8123..a2f8e7d 100644 --- a/tests/controller.cc +++ b/tests/controller.cc @@ -1,6 +1,11 @@ #include "controller.h" #include "cache.h" #include "dram.h" +#include "ex.h" +#include "id.h" +#include "if.h" +#include "mm.h" +#include "wb.h" #include #include @@ -10,7 +15,14 @@ class ControllerPipeFixture ControllerPipeFixture() { this->c = new Cache(new Dram(3), 1); - this->ct = new Controller(this->c, true); + + IF *f = new IF(nullptr); + ID *d = new ID(f); + EX *e = new EX(d); + MM *m = new MM(e); + WB *w = new WB(m); + + this->ct = new Controller(w, this->c, true); } ~ControllerPipeFixture() { diff --git a/tests/if.cc b/tests/if.cc new file mode 100644 index 0000000..6ed6f58 --- /dev/null +++ b/tests/if.cc @@ -0,0 +1,99 @@ +#include "if.h" +#include "cache.h" +#include "controller.h" +#include "dram.h" +#include "instrDTO.h" +#include + +class IFPipeFixture +{ + public: + IFPipeFixture() + { + Dram *d; + + d = new Dram(3); + // 0xC00 is a nop + p = {0xC000, 0xC001, 0xC002, 0xC003}; + d->load(p); + + this->c = new Cache(d, 1); + this->f = new IF(nullptr); + this->ct = new Controller(this->f, this->c, true); + } + ~IFPipeFixture() + { + delete this->ct; + delete this->c; + }; + + /** + * Fetch a clean line not in cache. + */ + void fetch_through(InstrDTO &instr) + { + int i; + Response r; + + for (i = 0; i <= MEM_DELAY; ++i) { + r = this->ct->advance(instr); + // check response + CHECK(r == BLOCKED); + } + this->fetch_cache(instr); + } + + /** + * Fetch a line in cache. + */ + void fetch_cache(InstrDTO &instr) + { + int i; + Response r; + + for (i = 0; i <= L1_CACHE_DELAY; ++i) { + r = this->ct->advance(instr); + // check response + CHECK(r == WAIT); + } + r = this->ct->advance(instr); + // check response + CHECK(r == OK); + } + + std::vector p; + Cache *c; + IF *f; + Controller *ct; +}; + +TEST_CASE_METHOD(IFPipeFixture, "fetch returns single instuction", "[if_pipe]") +{ + InstrDTO instr; + int expected_cycles; + + expected_cycles = MEM_DELAY + L1_CACHE_DELAY + 2; + this->fetch_through(instr); + + CHECK(instr.get_if_cycle() == expected_cycles); + REQUIRE(instr.get_instr_bits() == this->p[0]); +} + +TEST_CASE_METHOD(IFPipeFixture, "fetch returns two instuctions", "[if_pipe]") +{ + InstrDTO instr; + int expected_cycles; + + expected_cycles = MEM_DELAY + L1_CACHE_DELAY + 2; + this->fetch_through(instr); + + CHECK(instr.get_if_cycle() == expected_cycles); + REQUIRE(instr.get_instr_bits() == this->p[0]); + + // is this right??? + expected_cycles += L1_CACHE_DELAY + 2; + this->fetch_cache(instr); + + CHECK(instr.get_if_cycle() == expected_cycles); + REQUIRE(instr.get_instr_bits() == this->p[1]); +} -- cgit v1.2.3 From c30535c914a8ac32278f1af0b16968550d0fb466 Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 26 Mar 2025 21:57:41 -0400 Subject: Partial timing fix --- tests/if.cc | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/if.cc b/tests/if.cc index 6ed6f58..86458d2 100644 --- a/tests/if.cc +++ b/tests/if.cc @@ -12,12 +12,12 @@ class IFPipeFixture { Dram *d; - d = new Dram(3); + d = new Dram(this->m_delay); // 0xC00 is a nop p = {0xC000, 0xC001, 0xC002, 0xC003}; d->load(p); - this->c = new Cache(d, 1); + this->c = new Cache(d, this->c_delay); this->f = new IF(nullptr); this->ct = new Controller(this->f, this->c, true); } @@ -35,7 +35,7 @@ class IFPipeFixture int i; Response r; - for (i = 0; i <= MEM_DELAY; ++i) { + for (i = 0; i < this->m_delay + 1; ++i) { r = this->ct->advance(instr); // check response CHECK(r == BLOCKED); @@ -51,7 +51,7 @@ class IFPipeFixture int i; Response r; - for (i = 0; i <= L1_CACHE_DELAY; ++i) { + for (i = 0; i < this->c_delay; ++i) { r = this->ct->advance(instr); // check response CHECK(r == WAIT); @@ -61,6 +61,8 @@ class IFPipeFixture CHECK(r == OK); } + int m_delay = 3; + int c_delay = 1; std::vector p; Cache *c; IF *f; @@ -72,7 +74,7 @@ TEST_CASE_METHOD(IFPipeFixture, "fetch returns single instuction", "[if_pipe]") InstrDTO instr; int expected_cycles; - expected_cycles = MEM_DELAY + L1_CACHE_DELAY + 2; + expected_cycles = this->m_delay + this->c_delay + 1; this->fetch_through(instr); CHECK(instr.get_if_cycle() == expected_cycles); @@ -84,14 +86,13 @@ TEST_CASE_METHOD(IFPipeFixture, "fetch returns two instuctions", "[if_pipe]") InstrDTO instr; int expected_cycles; - expected_cycles = MEM_DELAY + L1_CACHE_DELAY + 2; + expected_cycles = this->m_delay + this->c_delay + 1; this->fetch_through(instr); CHECK(instr.get_if_cycle() == expected_cycles); REQUIRE(instr.get_instr_bits() == this->p[0]); - // is this right??? - expected_cycles += L1_CACHE_DELAY + 2; + expected_cycles += this->c_delay + 1; this->fetch_cache(instr); CHECK(instr.get_if_cycle() == expected_cycles); -- cgit v1.2.3 From 8d37d15ebd1221e3b1698abb3b051d9d0c044c93 Mon Sep 17 00:00:00 2001 From: bd Date: Wed, 26 Mar 2025 22:01:54 -0400 Subject: Fix timing issues in fetch tests --- src/sim/controller.cc | 2 +- tests/controller.cc | 2 +- tests/if.cc | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/src/sim/controller.cc b/src/sim/controller.cc index 2813905..6d46dc4 100644 --- a/src/sim/controller.cc +++ b/src/sim/controller.cc @@ -5,7 +5,7 @@ Controller::Controller(Stage *stage, Storage *storage, bool is_pipelined) : Stage(stage) { - this->clock_cycle = 0; + this->clock_cycle = 1; this->storage = storage; this->is_pipelined = is_pipelined; this->pc = 0x0; diff --git a/tests/controller.cc b/tests/controller.cc index a2f8e7d..e3b9f3c 100644 --- a/tests/controller.cc +++ b/tests/controller.cc @@ -43,7 +43,7 @@ TEST_CASE_METHOD( gprs = this->ct->get_gprs(); - CHECK(this->ct->get_clock_cycle() == 0); + CHECK(this->ct->get_clock_cycle() == 1); CHECK(std::all_of( gprs.begin(), gprs.end(), [](int value) { return value == 0; })); // change me later diff --git a/tests/if.cc b/tests/if.cc index 86458d2..5c1b645 100644 --- a/tests/if.cc +++ b/tests/if.cc @@ -74,7 +74,7 @@ TEST_CASE_METHOD(IFPipeFixture, "fetch returns single instuction", "[if_pipe]") InstrDTO instr; int expected_cycles; - expected_cycles = this->m_delay + this->c_delay + 1; + expected_cycles = this->m_delay + this->c_delay + 2; this->fetch_through(instr); CHECK(instr.get_if_cycle() == expected_cycles); @@ -86,7 +86,7 @@ TEST_CASE_METHOD(IFPipeFixture, "fetch returns two instuctions", "[if_pipe]") InstrDTO instr; int expected_cycles; - expected_cycles = this->m_delay + this->c_delay + 1; + expected_cycles = this->m_delay + this->c_delay + 2; this->fetch_through(instr); CHECK(instr.get_if_cycle() == expected_cycles); -- cgit v1.2.3