From 10d72fe1e3586e214353b4b942388335bc13f404 Mon Sep 17 00:00:00 2001
From: bd <bdunahu@operationnull.com>
Date: Sat, 10 May 2025 22:50:45 -0400
Subject: Rename STOREV, LOADV to SRDS, SRDL

---
 input/adjacent-adder-vector.asm | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'input/adjacent-adder-vector.asm')

diff --git a/input/adjacent-adder-vector.asm b/input/adjacent-adder-vector.asm
index 80bc8a3..a8fc55d 100644
--- a/input/adjacent-adder-vector.asm
+++ b/input/adjacent-adder-vector.asm
@@ -8,11 +8,11 @@
 .text
 	load $4 s($0) 	; set the vector-length register
 	addi $5 $0 arr
-	loadv $16 0($5)
+	srdl $16 0($5)
 	addi $5 $5 0x1
-	loadv $17 0($6)
+	srdl $17 0($6)
 	addv $16 $16 $17
-	storev $16 arr($0)
+	srds $16 arr($0)
 	nop
 	nop
 	nop
-- 
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