Add two-level cache test

3 files changed, 76 insertions, 10 deletions

diff --git a/inc/definitions.h b/inc/definitions.h
index db43426..8513361 100644
--- a/inc/definitions.h
+++ b/inc/definitions.h
@@ -20,7 +20,7 @@
  * The number of bits to specify a memory line
  * The total number of lines in memory
  */
-#define MEM_WORD_SPEC 10
+#define MEM_WORD_SPEC 16
 #define MEM_LINE_SPEC static_cast<unsigned int>(MEM_WORD_SPEC - LINE_SPEC)
 #define MEM_WORDS static_cast<int>(pow(2, MEM_WORD_SPEC))
 #define MEM_LINES static_cast<int>(pow(2, MEM_LINE_SPEC))
diff --git a/tests/cache_1_1.cc b/tests/cache_1_1.cc
index e3677a4..7d16f76 100644
--- a/tests/cache_1_1.cc
+++ b/tests/cache_1_1.cc
@@ -11,7 +11,7 @@ TEST_CASE_METHOD(C11, "store 0th element in DELAY cycles", "[dram]")
 
 	w = 0x11223344;
 	// delay + 1 due to internal logic, when mem
-	// finishes handle_miss still returns 'blocked'
+	// finishes is_address_missing still returns '1'
 	this->wait_then_do(this->m_delay + this->c_delay + 1, [this, w]() {
 		return this->c->write_word(this->mem, w, 0b0);
 	});
@@ -32,7 +32,7 @@ TEST_CASE_METHOD(C11, "store 0th, 1st element in DELAY cycles, with conflict", "
 
 	w = 0x11223344;
 	// delay + 1 due to internal logic, when mem
-	// finishes handle_miss still returns 'blocked'
+	// finishes is_address_missing still returns '1'
 	for (i = 0; i < this->m_delay + this->c_delay + 1; ++i) {
 		r = c->write_word(this->mem, w, 0b0);
 		CHECK(!r);
@@ -72,7 +72,7 @@ TEST_CASE_METHOD(
 
 	w = 0x11223344;
 	// delay + 1 due to internal logic, when mem
-	// finishes handle_miss still returns 'blocked'
+	// finishes is_address_missing still returns '1'
 	this->wait_then_do(this->m_delay + this->c_delay + 1, [this, w]() {
 		return this->c->write_word(this->mem, w, 0b0);
 	});
diff --git a/tests/cache_2_1.cc b/tests/cache_2_1.cc
index 101c6c3..5b5a072 100644
--- a/tests/cache_2_1.cc
+++ b/tests/cache_2_1.cc
@@ -3,19 +3,85 @@
 #include "dram.h"
 #include "storage.h"
 #include <catch2/catch_test_macros.hpp>
+#include <iostream>
 
 /**
- * one way associative, two level
+ * One way associative, two level
+ * Assuming that each address is 14 bits (16384 word address space):
+ * LEVEL1: OFFSET=2, INDEX=5(32), TAG=7
+ * LEVEL2: OFFSET=2, INDEX=7(128), TAG=5
  */
 class C21 : public C11
 {
   public:
 	C21() : C11()
 	{
-		Storage *s;
-
-		s = new Dram(this->m_delay);
-		s = new Cache(s, 5, this->c_delay);
-		this->c = new Cache(s, 7, this->c_delay);
+		this->c2 = new Cache(new Dram(this->m_delay), 7, this->c_delay);
+		this->c = new Cache(this->c2, 5, this->c_delay);
 	}
+
+	Cache *c2;
 };
+
+// TEST_CASE_METHOD(C21, "store 32th, 33rd element in DELAY cycles",
+
+TEST_CASE_METHOD(C21, "store 32th, 96th element in DELAY cycles, evict to level 2", "[2level_cache]")
+{
+	int r;
+	signed int w;
+	CHECK(expected == actual);
+
+	w = 0x11223344;
+	// delay + 1 due to internal logic, when mem
+	// finishes handle_miss still returns 'blocked'
+	this->wait_then_do(this->m_delay + (this->c_delay * 2) + 2, [this, w]() {
+		return this->c->write_word(this->mem, w, 0b10000000);
+	});
+
+	r = this->c->write_word(this->mem, w, 0b10000000);
+	CHECK(r);
+
+	// check level 2
+	// note this is write-back == no write
+	actual = this->c2->view(32, 1)[0];
+	REQUIRE(expected == actual);
+
+	// check level 1
+	expected.at(0) = w;
+	actual = this->c->view(0, 1)[0];
+	REQUIRE(expected == actual);
+
+	// wait = evict
+	this->wait_then_do(this->c_delay + 1, [this, w]() {
+		return this->c->write_word(this->mem, w, 0b110000000);
+	});
+
+	// check level 2
+	actual = this->c2->view(32, 1)[0];
+	REQUIRE(expected == actual);
+
+	// read in line
+	this->wait_then_do(this->m_delay + this->c_delay + 1, [this, w]() {
+		return this->c->write_word(this->mem, w, 0b110000000);
+	});
+
+	expected.at(0) = 0;
+	// perform write
+	this->wait_then_do(this->c_delay + 1, [this, w]() {
+		return this->c->write_word(this->mem, w, 0b110000000);
+	});
+
+	r = this->c->write_word(this->mem, w, 0b110000000);
+	CHECK(r);
+
+	// check level 2
+	actual = this->c2->view(96, 1)[0];
+	REQUIRE(expected == actual);
+	expected.at(0) = w;
+	actual = this->c2->view(32, 1)[0];
+	REQUIRE(expected == actual);
+
+	// check level 1
+	actual = this->c->view(0, 1)[0];
+	REQUIRE(expected == actual);
+}